Intel Corporation

Advanced Micro Devices Corporation

Altera Corporation

Fujitsu Corporation

Globalfoundries Inc.

Stmicroelectronics S.r.l.

Ravi Prakash Gutala

Aravind Raghavendra Dasu

Scott J Weber

Colin Stewart Bill

Jonathan S Su

Kevin Clark

Eriko Nurvitadhi

Sean R Atsatt

Sameer S Haddad

Mahesh A Iyer

James Loran Ball

Ravi S Sunkavalli

Jun Pin Tan

Wing Han Leung

Karthik Chandrasekar

Archanna Srinivasan

John Chen

Robert L Sankman

Debendra Mallik

Ravindranath Vithal Mahajan

Rajat Agarwal

Dheeraj R Subbareddy

Md Altaf Hossain

Ankireddy Nalamalpu

Ram S Viswanath

Sandeep B Sane

Sriram Srinivasan

Ferdinando Bedeschi

Vei-Han Chan

Simon S Chong

Wendemagegnehu Beyene

Guang Chen

Vei-Han Chen

Martin Langhammer

Jawad Basit Khan

Arifur Rahman

Takao Akaogi

Chi K Chang

Andy T Nguyen

Michael Allen Van Buskirk

Pau-Ling Chen

Binh Quang Le

Richard L Coulson

Shane Charles Hollmer

Albert Fazio

Ilya K Ganusov

David J Greenhill

Devdatta P Kulkarni

Johnny Javanifard

Chung-You Hu

Enzo M Donze

Joseph G Pawletko

Rich Fackenthal

Matthew I Adiletta

Kuldeep Amarnath

Anthony Suk Ko

Jonathan Shi-Chang Su

Arif Rahman

Shreepad Panth

Thomas Sarvey

Kevin W Plouse

Qimeng (Derek) Zhou

Qimeng Derek Zhou

Terence Magee

Meenatchi Jagasivmani

An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.

Multi-purpose interface for configuration data and user fabric data

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

Interconnect architecture with silicon interposer and EMIB

A circuit system includes a power control circuit that generates multiple voltage identifiers. Multiple voltage regulator circuits generate multiple supply voltages based on the voltage identifiers. The supply voltages are provided to multiple integrated circuit dies. The power control circuit varies the voltage identifiers based on changes in metrics associated with the integrated circuit dies to cause the voltage regulator circuits to vary the supply voltages. Integrated circuit dies receive supply voltages from voltage regulator circuits through power delivery networks. The integrated circuit dies provide voltage sense signals that indicates the supply voltages. The voltage regulator circuits adjust the supply voltages based on the voltage sense signals to compensate for voltage drops in the power delivery networks.

Supply voltage control systems and methods for integrated circuits

This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

System-in-package network processors

A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.

Circuit systems and methods for reducing power supply voltage droop

A circuit system includes a first voltage regulator circuit that generates a first supply voltage for an integrated circuit die based on a first control signal. The first voltage regulator circuit generates a first feedback signal based on the first supply voltage. The circuit system also includes a second voltage regulator circuit that generates a second supply voltage for an integrated circuit die based on a second control signal. The second voltage regulator circuit generates a second feedback signal based on the second supply voltage. The circuit system also includes a third voltage regulator circuit that generates the first control signal based on the first feedback signal and the second control signal based on the second feedback signal. The circuit system may include fully integrated, on-board, and on-package voltage regulator circuits.

Voltage regulator circuit systems and methods

An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.

Compute-in-memory systems and methods

An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.

Embedded network on chip accessible to programmable logic fabric of programmable logic device in multi-dimensional die systems

A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

Three dimensional circuit systems and methods having memory hierarchies

An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.

Integrated circuit device with separate die for programmable fabric and programmable fabric support circuitry

Growing community of inventors

San Jose, CA, United States of America

Ravi Prakash Gutala