Intel Corporation

Google Inc.

Sony Group Corporation

Santa Clara

Ravi Pillarisetty

Jack T Kavalieros

Marko Radosavljevic

Gilbert W Dewey

Willy Rachmady

Robert S Chau

Niloy Mukherjee

Van H Le

Benjamin Chu-Kung

James S Clarke

Jeanette M Roberts

Abhishek A Sharma

Prashant Majhi

Brian S Doyle

Han Wui Then

Hubert C George

Elijah V Karpov

Nicole K Thomas

Matthew V Metz

Zachary R Yoscovits

David J Michalak

Uday Shah

Roman Caudillo

Sansaptak W Dasgupta

Lester Lampert

Seung Hoon Sung

Mantu K Hudait

Kanwaljit Singh

Titash Rakshit

Niti Goel

Roza Kotlyar

Jessica S Kachian

Sanaz Kabehie Gardner

Been-Yih Jin

Charles C Kuo

Harold W Kennel

Tahir Ghani

Patrick R Morrow

Rishabh Mehandru

Nancy M Zelick

Stephanie A Bojarski

Adel A Elsherbini

Aaron D Lilak

Cheng-Ying Huang

Christopher J Jezewski

Shriram Shivaraman

Martin D Giles

Aaron A Budrevich

Valluri Ramana Rao

Kimin Jun

Scott Bruce Clendenning

Patrick H Keys

Jessica M Torres

Sasikanth Manipatruni

Anand S Murthy

Ian A Young

Suman Datta

Glenn A Glass

Stephen M Cea

Kaan Oguz

Hui Jae Yoo

Stefano Pellerano

Ashish Agrawal

Mark Y Liu

Satyarth Suri

Justin Brockman

Johanna M Swan

Dmitri E Nikonov

Uygar E Avci

Paul B Fischer

John Stephen Guzek

Robert L Bristol

David L Kencke

Ilya V Karpov

Sairam Agraharam

Anh Phan

Markus Kuhn

Tristan A Tronic

Brennen Karl Mueller

Mark L Doczy

Shawna M Liff

Ram K Krishnamurthy

Rafael Rios

Dinesh Somasekhar

Kevin O'Brien

Islam A Salama

Raghavan Kumar

Gregory Kengho Chen

Yih Wang

Wilman Tsai

Phil Knag

Nick Lindert

Rami Hourani

Huseyin Ekin Sumbul

Sean W King

Miriam Ruth Reshotko

Jason W Klaus

Tejaswi K Indukuri

Anup Pancholi

Jeffery D Bielefeld

Technologies for radiofrequency optimized interconnects for a quantum processor are disclosed. In the illustrative embodiment, signals are carried in coplanar waveguides on a surface of a quantum processor die. A ground ring surrounds the signals and is connected to the ground conductors of each coplanar waveguide. Wire bonds connect the ground ring to a ground of a circuit board. The wire bonds provide both an electrical connection from the quantum processor die to the circuit board as well as increased thermal coupling between the quantum processor die and the circuit board, increasing cooling of the quantum processor die.

Technologies for radio frequency optimized interconnects for a quantum processor

An array of spin qubits relies on a gradient magnetic field to ensure that the qubits are separated in frequency in order to be individually addressable. Furthermore, a strong magnetic field gradient is required to electrically drive the EDSR of the qubits. Quantum dot devices and related methods and systems that integrate magnetic materials in the gates to provide a gradient magnetic field are disclosed. Magnetic materials in different gates may be of different heights to improve frequency separation of neighboring qubits. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein may enable improved control over magnetic fields and their gradients to realize better frequency targeting of individual qubits, help minimize adverse effects of charge noise on qubit decoherence and provide good scalability in the number of quantum dots included in the device.

Quantum dot devices with magnetic gates

Quantum dot devices and related methods and systems that use semiconductor nanoribbons arranged in a grid where a plurality of first nanoribbons, substantially parallel to one another, intersect a plurality of second nanoribbons, also substantially parallel to one another but at an angle with respect to the first nanoribbons, are disclosed. Different gates at least partially wrap around individual portions of the first and second nanoribbons, and at least some of the gates are provided at intersections of the first and second nanoribbons. Unlike previous approaches to quantum dot formation and manipulation, nanoribbon-based quantum dot devices provide strong spatial localization of the quantum dots, good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.

Nanoribbon-based quantum dot devices

A backend electrostatic discharge (ESD) diode device structure is presented comprising: a first structure comprising a first material, wherein the first material includes metal; a second structure adjacent to the first structure, wherein the second structure comprises a second material, wherein the second material includes a semiconductor or an oxide; and a third structure adjacent to the second structure, wherein the third structure comprises the first material, wherein the second structure is between the first and third structures.

Backend electrostatic discharge diode apparatus and method of fabricating the same

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.

Quantum dot array devices with shared gates

Quantum circuit assemblies that employ active pulse shaping in order to be able to control states of a plurality of qubits with signal pulses propagated over a shared signal propagation channel are disclosed. An example quantum circuit assembly includes a quantum circuit component that includes a first qubit, associated with a first frequency to control the state of the first qubit, and a second qubit, associated with a second frequency to control the state of the second qubit. A shared transmission channel is coupled to the first and second qubits. The assembly further includes a signal pulse generation circuit, configured to generate a signal pulse to be propagated over the shared transmission channel to control the state of the first qubit, where the signal pulse has a center frequency at the first frequency, a bandwidth that includes the second frequency, and a notch at the second frequency.

Scalable gate control in quantum circuit assemblies

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

Quantum dot devices with fins

Disclosed herein are lateral gate material arrangements for quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; and a gate above the quantum well stack, wherein the gate includes a gate electrode, the gate electrode includes a first material proximate to side faces of the gate and a second material proximate to a center of the gate, and the first material has a different material composition than the second material.

Lateral gate material arrangements for quantum dot devices

Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.

Quantum dot devices

Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

Self-aligned contacts for thin film transistors

A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. A channel nanowire having a third lattice is formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. A gate dielectric layer is formed on and all-around the channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.

Non-planar gate all-around device and method of fabrication thereof

A stacked-substrate FPGA device is described in which a second substrate is stacked over a first substrate. Logic transistors (e.g., semiconductor devices and at least some conductive interconnections between them) are generally fabricated on (or over) a first substrate and memory transistors (e.g., SRAM cells and SRAM arrays) are generally fabricated on a second substrate over the first substrate. This has the effect of physically disposing elements of a CLB and a programmable switch on two different substrates. That is a first portion of a CLB and a programmable switch corresponding to logic transistors are on a first substrate and a second portion of these components of an FPGA corresponding to SRAM transistors is on a second substrate.

Stacked-substrate FPGA semiconductor devices

Quantum dot devices with independent gate control are disclosed. An example quantum dot device includes N parallel rows of gate lines provided over a quantum well stack. Each of the N parallel rows of gate lines defines a respective row of a quantum dot formation region in the quantum well stack and includes M parallel gate lines stacked above one another. The quantum dot device may further include, for each of the N×M gate lines, a gate that extends toward the quantum well stack, where, for an individual row of the N parallel rows, gates that extend toward the quantum well stack from the M parallel stacked gate lines are arranged above a respective row of a quantum dot formation region in the quantum well stack. In this manner, each of the N×M gates responsible for formation of different quantum dots may be controlled independently.

Quantum dot devices with independent gate control

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

Quantum dot devices with overlapping gates

Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.

Non-silicon N-type and P-type stacked transistors for integrated circuit devices

Growing community of inventors

Portland, OR, United States of America

Ravi Pillarisetty