International Business Machines Corporation

Ravi Nair

Hans Mikael Jacobson

Bruce Martin Fleischer

Thomas Winters Fox

James Allan Kahle

Daniel Arthur Prener

Charles Ray Johns

Pradip Bose

Harm Peter Hofstee

Hillery C Hunter

Sumedh Wasudeo Sathaye

Kathryn Mary O'Brien

John Kevin O'Brien

Erik Richter Altman

Peter Howland Oden

Michael K Gschwind

John-David Wellman

Constantinos Evangelinos

Chen-Yong Cher

Jaime Humberto Moreno

Philip Heidelberger

Martin Ohmacht

Peter George Capek

Alper Buyuktosunoglu

Zehra Noman Sura

Changhoan Kim

Bahman Hekmatshoartabari

Hung Qui Le

Hubertus Franke

Arvind Kumar

Harold Wade Cain, Iii

Krishnan Sugavanam

Robert Alan Philhower

John K P O'Brien

Arpith C Jacob

Wolfram Sauer

Patrick D Siegl

Kevin John Patrick O'Brien

Alexander Reznicek

Li Feng Zhang

Mukta G Farooq

Michael Rizzolo

Sang Hoo Dhong

Ashish Kundu

Vijayalakshmi Srinivasan

Hong Min

Richard James Eickemeyer

Masakazu Suzuoki

James Patrick Smith

Petr Novotny

Kevin Alexander Stoodley

Shyam Ramji

Motohiro Kawahito

Qi Zhang

Takuya Nakaike

Wing Kin Luk

Ming Tan

Swagath Venkataramani

Krishnan Kunjunny Kailas

Charles Roberts Moore

Augusto Javier Vega

Saloni Potdar

Lei Yu

Bryan Savoye Rosenburg

Haoyu Wang

Raymond Cheung Yeung

Jose R Brunheroto

Yang Yu

Takeshi Yamazaki

James C Sexton

Martin Edward Hopkins

Abdullah Kayi

Suyog Gupta

Prashant Jayaprakash Nair

Wolfram M Sauer

Seokin Hong

Steven Douglas Posluszny

Sumeda Wasudeo Sathaye

A processor core includes a storage device which stores a composite very large instruction word (VLIW) instruction, an instruction unit which obtains the composite VLIW instruction from the storage device and decodes the composite VLIW instruction to determine an operation to perform, and a composite VLIW instruction execution unit which executes the composite VLIW instruction to perform the operation.

Executing a composite scalar-vector VLIW instruction having a repeat field

A memory system, a method of assembling the memory system, and a computer system. The memory system includes a global memory device coupled to a plurality of processing elements. The global memory device is positioned external to a chip on which the plurality of processing devices reside. The memory system also includes at least one main scratchpad coupled to the at least one processing element of the plurality of processing devices and the global memory device. The memory system further includes a plurality of auxiliary scratchpads coupled to the plurality of processing elements and the global memory device. The one or more auxiliary scratchpads are configured to store static tensors. At least a portion of the plurality of auxiliary scratchpads are configured as a unitary multichannel device.

Multichannel memory to augment local memory

A multichip module with a vertical stack of a logic chip, a translator chip, and at least one memory chip. The multichip module includes a logic chip, a translator chip over and vertically connecting to the logic chip, and at least one memory chip above and vertically connecting to the translator chip where the translator chip is one of a chip with active devices or a passive chip.

Memory and logic chip stack with a translator chip

Techniques for refinement of data pipelines are provided. An original file of serialized objects is received, and an original pipeline comprising a plurality of transformations is identified based on the original file. A first computing cost is determined for a first transformation of the plurality of transformations. The first transformation is modified using a predefined optimization, and a second cost of the modified first transformation is determined. Upon determining that the second cost is lower than the first cost, the first transformation is replaced, in the original pipeline, with the optimized first transformation.

Streamlining data processing optimizations for machine learning workloads

A memory device is provided that includes at least one MTJ pillar which can have a ternary program state as compared to a binary program state in a conventional device. The MTJ pillar contains a lower MTJ structure that includes at least a first magnetic reference material, a first tunnel barrier and a first magnetic free layer material, and an upper MTJ structure that includes at least a second magnetic reference material, a second tunnel barrier and a second magnetic free layer material; the upper MTJ structure is stacked atop the lower MTJ structure. The first and second magnetic free layer materials have different designs and/or compositions resulting in different switching voltages.

MRAM structure with ternary weight storage

A memory network can be constructed with at least memory write weightings, memory read weightings and at least one read vector, the memory write weightings parameterizing memory write operations of a neural network to the memory matrix, the memory read weightings parameterizing memory read operations of the neural network from the memory matrix. At least one of the write weightings, the read weightings, or elements of the at least one read vector, can be initialized to have sparsity and/or low discrepancy sampling pattern. The memory network can be trained to perform a task.

Initialization of memory networks

A method of text classification includes generating a text embedding vector representing a text sample and applying weights of a regression layer to the text embedding vector to generate a first data model output vector. The method also includes generating a plurality of prototype embedding vectors associated with a respective classification labels and comparing the plurality of prototype embedding vectors to the text embedding vector to generate a second data model output vector. The method further includes assigning a particular classification label to the text sample based on the first data model output vector, the second data model output vector, and one or more weighting values.

Hybrid model for short text classification with imbalanced data

An approach is described that provides access to a named data element in a Coordination Namespace that is stored in a memory that is distributed amongst a set of nodes. A request of a name corresponding to the named data element is received from a requesting process and the approach responsively searches for the name in the Coordination Namespace. In response to determining an absence of data corresponding to the named data element, a pending state is indicated to the requesting process. In response to determining that the data corresponding to the named data element exists, a successful state is returned to the requesting process. In one embodiment, the successful state also includes providing the requesting process with access to the data corresponding to the named data element.

Access of named data elements in coordination namespace

A computer system includes a processor, main memory, and controller. The processor includes a plurality of hardware threads configured to execute a plurality of software threads. The main memory includes a first register table configured to contain a current set of architected registers for the currently running software threads. The controller is configured to change a first number of the architected registers assigned to a given one of the software threads to a second number of architected registers when a result of monitoring current usage of the registers by the software threads indicates that the change will improve performance of the computer system. The processor includes a second register table configured to contain a subset of the architected registers and a mapping table for each software thread indicating whether the architected registers referenced by the corresponding software thread are located in the first register table or the second register table.

Dynamic update of the number of architected registers assigned to software threads using spill counts

An approach is disclosed that relocates a named data element. A request to move a name corresponding to the named data element is received from a first storage area in a Coordination Namespace to a second storage area in the Coordination Namespace. The first storage area has a first level of persistence, and the second storage area has a second level of persistence. The named data element exists in a Coordination Namespace that is allocated in a memory distributed amongst a plurality of nodes that include the local node and one or more remote nodes. The approach then creates a copy of the named data element in the second storage area.

Relocation and persistence of named data elements in coordination namespace

Embodiments for mitigating cache-based data security vulnerabilities in a computing environment are provided. Cache pollution due to speculative memory accesses within a speculative path is avoided by delaying data updates to a cache and memory subsystem until the speculative memory accesses are resolved. A speculative buffer is used to maintain the speculative memory accesses such that a state of the cache remains unchanged until the speculative memory accesses are committed.

Microarchitectural techniques to mitigate cache-based data security vulnerabilities

An approach is described that provides a distributed directory structure within a storage of an information handling system (a local node). A request is received with the request corresponding to a shared virtual address. The shared virtual address that is shared amongst a number of nodes that includes the local node and some remote nodes. A Global Address Space Directory (GASD) is retrieved that corresponds to a global virtual address space. The GASD is stored in a Coordination Namespace that is stored in a memory that is distributed amongst the nodes. A mapping that is included in the GASD is used to determine the node where the shared virtual address currently resides. The shared virtual address is then accessed from the node where it currently resides.

Distributed directory of named data elements in coordination namespace

An approach is described that accesses data in a shared memory that is shared amongst nodes that include a local node and remote nodes. The local node receives a name corresponding to a named data element in a Coordination Namespace, the Coordination Namespace having been created in a memory distributed amongst the nodes. A hash function is applied to at least a portion of the name with a result of the hash function being a natural node indicator. Data corresponding to the named data element is requested from a natural node identified by the indicator. Based on the request, a response is received from the natural node.

Coordination namespace processing

Embodiments for implementing partial synchronization between compute processes based on threshold specification in a computing environment. One or more compute processes may be synchronized in one of a plurality of types of computing platforms using a barrier having a barrier release condition based on a threshold of one or more measures. The barrier is defined according to one or more parameters. The one or more compute processes may be released via the barrier upon exceeding the threshold of the one or more measures.

Partial synchronization between compute tasks based on threshold specification in a computing system

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Briarcliff Manor, NY, United States of America

Ravi Nair