Xilinx, Inc.

Achronix Semiconductor Corporation

Other

Ravi Nagarajarao Kurlagunda

Ravi S Sunkavalli

Chandrasekhar S Thyamagondlu

Rahul Nimaiyar

Vijay Bantval

Ellery Cochell

Sonal Santan

Brian S Martin

Kenneth Chan

Sebastian Turullols

Hem C Neema

David A Knol

Stephen P Rozum

Pradip Jha

Ravinder Sharma

Sudipto Chakraborty

Dinesh K Monga

Cheng Zhen

Ch Vamshi Krishna

Lizhi Hou

Kaustuv Manji

Min Ma

Rohini Raghunathan

Manjunath Chepuri

Pranjal Joshi

Karen Xie

Amit Kumar

Himanshu Choudhary

A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

High throughput circuit architecture for hardware acceleration

Secure updating of programmable integrated circuits includes receiving, within the programmable integrated circuit, a configuration bitstream, inserting, using a processor of the programmable integrated circuit, a key into the configuration bitstream resulting in a modified configuration bitstream, encrypting, using the programmable integrated circuit, the modified configuration bitstream using the key resulting in an encrypted configuration bitstream, and storing the encrypted configuration bitstream in a boot memory for the programmable integrated circuit.

Secure update of programmable integrated circuits in data center computing environments

Bootstrapping a programmable integrated circuit (IC) based network interface card (NIC) can include implementing, within the programmable IC, a first circuitry by loading a first stage configuration bitstream, wherein the first circuitry includes a bus endpoint configured to communicate with a host computer via a communication bus, a platform processor, and a first bootloader. The platform processor, executing the first bootloader, loads a first firmware within the programmable IC. A second circuitry is implemented within the programmable IC by the platform processor executing the first firmware to load a second stage configuration bitstream. The second circuitry includes a NIC controller. The platform processor, executing the first firmware, loads a second firmware within the programmable IC. The second firmware is executable to configure the second circuitry.

Bootstrapping a programmable integrated circuit based network interface card

A device includes a platform implemented, at least in part, in a static region of programmable circuitry and a dynamic region of programmable circuitry configured to implement user-specified circuitry in communication with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of programmable circuitry is dynamically reconfigured.

Dynamically reconfigurable networking using a programmable integrated circuit

A system includes a host system and an integrated circuit coupled to the host system through a communication interface. The integrated circuit is configured for hardware acceleration. The integrated circuit includes a direct memory access circuit coupled to the communication interface, a kernel circuit, and a stream traffic manager circuit coupled to the direct memory access circuit and the kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the host system and the kernel circuit.

Streaming platform flow and architecture for an integrated circuit

An integrated circuit (IC) includes a first kernel circuit implemented in programmable circuitry, a second kernel circuit implemented in programmable circuitry, and a stream traffic manager circuit coupled to the first kernel circuit and the second kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the first kernel circuit and the second kernel circuit.

Streaming platform architecture for inter-kernel circuit communication for an integrated circuit

A photovoltaic electric vehicle charging system includes an enclosure to receive photovoltaic panels and the photovoltaic panels connected to each other via a plurality of connecting members inside the enclosure. A sliding mechanism moves panels in and out of the enclosure and the enclosure is configured to be mounted on a vehicle or embedded within the vehicle.

Vehicle attached photovoltaic charging systems

Constraint handling for a circuit design may include determining, using a processor, instances of parameterizable modules of a circuit design associated with constraints based upon a predefined hardware description language attribute within the instances, extracting, using the processor, parameter values from the instances of the parameterizable modules, and generating, using the processor, static constraint files for the instances of the parameterizable modules using the extracted parameter values.

Constraint handling for parameterizable hardware description language

Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.

Hierarchical global clock tree

Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. One or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.

Reset signal distribution

Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.

Growing community of inventors

Fremont, CA, United States of America

Ravi Nagarajarao Kurlagunda