Intel Corporation

Other

Ravi Nagaraj

Neil W Songer

Frank P Hart

James L Noble

Gary A Solomon

James E Akiyama

Gurbir Singh

Xia Dai

Pochang Hsu

Jerald N Hall

Cau L Nguyen

Edwin J Pole, Ii

John T Orton

Kirk Tyler Byers

Peter A Ward

Jesse Treger

Aniruddha Kunda

A thermal sensing system allowing the measurement of the temperature of multiple integrated circuit devices using a single thermal sensor. The thermal sensor is positioned proximally to a first integrated circuit device to obtain ambient temperature readings from the device. The thermal sensor also includes remote sensing capability to measure the temperature of a second integrated circuit device positioned away from the thermal sensor. The thermal sensing system may be used to monitor a microprocessor module for an overheat condition and respond accordingly.

Thermal sensing of multiple integrated circuits

A processor has an external pin that can be asserted to lock in new clock ratio information dynamically. A state machine of the processor defines a stop grant state that is utilized to halt the internal clocking signal of the processor. A storage location, such as a register, is utilized to load new clock frequency information into the clock generator circuit of the processor. De-asserting the external pin of the processor causes the processor to resume normal operations, but at the newly set clock frequency.

Apparatus and method for changing processor clock ratio settings

A dual mode I/O interface circuit compatible with either GTL logic signals or traditional CMOS logic signals comprises a connection node with a differential sense amplifier having one input coupled to the connection node, and the other input coupled to a reference voltage. Pull-up and pull-down circuits are coupled to the connection node. Logic circuitry is coupled to the gate of the at least one P-type field-effect transistor of the pull-up circuit, and the gate of the at least one N-type field-effect transistor of the pull-down circuit to control the conductivity of the field-effect transistors. In this manner, a first representation of the input signal compatible with GTL logic signals as provided at the connection node when the mode signal is asserted, and a second representation of the input signal compatible with CMOS logic levels as provided at the connection node when the mode signal is deasserted.

Dual mode input/output interface circuit

A method and apparatus for providing a wave-table upgrade card to a baseboard having integrated audio card capabilities. The baseboard with the integrated audio features is provided with a connector with a predetermined header that is adapted to be coupled to a wave-table upgrade card through a plurality of data conductors. The wave-table upgrade card is provided with a connector having the same predetermined header as the connector on the baseboard. The predetermined header for the connectors and the data conductors includes a MIDI.sub.-- Out pin, a Wave.sub.-- Right pin, a Wave.sub.-- Left pin, a MIDI.sub.-- In pin, at least one ground pin, and a physical key that prevents improper insertion of the data conductors into the connectors on the wave-table card and baseboard.

Motherboard solution for wave table upgrade

A method and apparatus for converting a signal from a first voltage level to a second voltage level before providing the signal to a processor. A circuit board includes an interface for coupling the circuit board to a peripheral subsystem via a socket. The circuit board also includes a processor that receives signals of a first voltage level, a first signal line, and a second signal line. The first signal line is coupled to the interface and provides a reference signal to the peripheral subsystem that indicates the first voltage level. The second signal line is also coupled to the interface and provides a subsystem signal back from the peripheral subsystem after the signal has been converted to the first voltage level.

Method and apparatus for providing a processor module for a computer

A method and apparatus for upgrading a computer system from one processor generation to another processor generation. The processor and its corresponding primary bridge are included together on the same circuit board. The circuit board has an interface which can be inserted into a socket of a system. The interface socket includes the memory bus and peripheral component bus from the bridge.

Method and apparatus for upgrading a computer system

Apparatus and method of assisting software emulation of hardware functions in a processor. During a read cycle on an address bus, an address that is within a predetermined address range is stored in a trap register and a Type-of-Cycle bit in the trap register is set to the read state. If an Issue-SMI-on-Next-Access bit in the trap register is set to the on state, a system management interrupt is issued to the processor. During a write cycle, data on the data bus is stored in a data field of the trap register, the address is stored in the address field of the trap register and the Type-of-Cycle bit is set to the write state. A system management interrupt is issued if the Issue-SMI-on-Next-Access bit is set to the on state. Then the Issue-SMI-on-Next-Access bit is set to the off state. The Type-of-Cycle bit of the trap register is set if the system management interrupt is detected at the processor. Data from the processor is placed into the data field of the trap register if the Type-of-Cycle bit is set to the read state. An I/O restart operation of the processor is then invoked. The Type-of-Cycle bit of the trap register is read if the system management interrupt is detected at the processor. Data from the processor is stored into the data field of the trap register if the Type-of-Cycle bit is set to the read state. An I/O restart operation of the processor is then invoked. The contents of the data field of the trap register are placed on the data bus if the Issue-SMI-on-Next-Access bit is set to the off state. Then the Issue-SMI-on-Next-Access bit is set to the on state.

Device to assist software emulation of hardware functions

An apparatus and method for enabling a Peripheral Component Interconnect ('PCI') bus to support direct memory access ('DMA') transfers. The apparatus comprises a plurality of DMA controllers, a state machine and an internal storage element. The plurality of DMA controllers transfers DMA requests for an electronic device to the state machine and DMA acknowledges from the state machine to the electronic device. The state machine controls the DMA transfer by performing two transactions for each DMA transfer; namely, a memory cycle and an input/output cycle. The internal storage element acts as a buffer for this multiple cycle DMA transfer.

Apparatus, system and method for supporting DMA transfers on a

A computer having a motherboard housed in a chassis having a bottom panel and a rear panel perpendicular to the bottom panel. The rear panel has a cutout therein. The motherboard is secured to the chassis in parallel with the bottom panel. The motherboard has a socket and the audio card is mounted in the socket perpendicular to the motherboard. The audio card has connectors, such as audio line-in, line-out, microphone, speaker power and game port, mounted perpendicular to the audio card such that the connectors are aligned with the cutout in the rear panel. The audio card is grounded to the chassis with an electromagnetic interference (EMI) gasket contoured to the cutout.

Growing community of inventors

Hillsboro, OR, United States of America

Ravi Nagaraj