Samsung Electronics Co., Ltd.

Nxp B.v.

Nxp Usa, Inc.

Ravi Kumar

Deependra Kumar Jain

Gaurav Agrawal

Krishna Thakur

Arun Kumar Singh

Ravichandar Reddy Geetla

Santosh Kumar

Milind Joshi

A multiphase digital frequency synthesizer including a multiphase ring oscillator that provides phased clock signals, a clock divider that divides a phased clock signal by an integer value and a carry value to provide a divided clock signal, positive select circuitry that determines and updates a positive select value with accumulation and a modulo function based on a fractional division factor updated with successive cycles of the divided clock signal, carry circuitry that determines the carry value based on a number of the phased clock signals, positive multiplex circuitry that selects from among the phased clock signal using the positive select value for providing a positive multiplexed clock signal, and fractional phase addition circuitry that provides a first output clock signal based on a selected phased clock signal, the divided clock signal, and the positive multiplexed clock signal. Similar negative select circuitry and duty cycle correction circuitry may be included.

Multiphase digital frequency synthesizer with fractional division

An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.

Circuitry and methods for fractional division of high-frequency clock signals

Disclosed is a method of displaying content on a glass window of a vehicle, including capturing sight information of surrounding scenery of the vehicle during a first time period, by using at least one first image capturing device, identifying a request for displaying content related to the sight information from a user during a second time period after the first time period, and displaying the content related to the sight information on the glass window of the vehicle based on the request.

Method and system of displaying multimedia content on glass window of vehicle

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Noida, India

Ravi Kumar