Qualcomm Incorporated

Ravi Kumar Sepuri

Santhosh Reddy Akavaram

Prakhar Srivastava

Ravindranath Doddi

Chintalapati Bharath Sai Varma

Umamaheshwaran V

Hung Vuong

Aditya Singh Patel

Khushboo Kumari

An integrated circuit (IC) device, implemented using chiplets mounted on a substrate, may include a controller and a first plurality of link modules. The first plurality of link modules may be configured to provide data lanes in a multimodule data communication link. The controller may be configured to retrain a failed link module in the first plurality of link modules while one or more other link modules in the first plurality of link modules are active and available for transmitting or receiving data, reconfigure the multimodule data communication link to use a second plurality of link modules that excludes the failed link module and includes fewer link modules than the first plurality of link modules, and reconfigure the multimodule data communication link to use the first plurality of link modules for transmitting or receiving the data after the failed link module has been successfully retrained.

Mechanism to enhance link bandwidth in interconnects

A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device and configured to receive a notification from the flash memory device that a performance threshold register value has been exceeded while the flash memory device is configured to use a shared write buffer. The HCI is also configured to, in response to receiving the notification, perform a remedial action that includes reassigning a portion of a first logical unit (LU).

Host management of flash memory with shared write buffer

A method for managing an interconnection between chiplets includes initiating sideband link training that includes transmitting a training pattern over each of a plurality of link configurations, where each link configuration includes a sideband data line and a sideband clock line. The method further includes suspending the sideband link training before completion of the sideband link training when the training pattern is transmitted over a first sideband link configuration without error, designating a sideband data line and a sideband clock line in the first sideband link configuration as a functional pair, and initiating mainband link training using the functional pair to communicate link state and status information.

Mechanism to improve link initialization time

The disclosed techniques store certain information of functional modules and lanes to optimize a die-to-die interconnect link. Based on the information, the apparatus can optimize a link width and a multi-module link configuration of the interconnect link. An integrated circuit device includes a first die, a second die, and a die-to-die (D2D) interconnect link connected between the first die and the second die. The D2D interconnect link includes a plurality of lanes grouped into a plurality of modules. The apparatus maintains a training result of the D2D interconnect link based on the training of the D2D interconnect link, the training result including one or more link configurations of the plurality of modules. The apparatus selects a link configuration of the one or more link configurations to configure the D2D interconnect link including one or more of the plurality of modules.

Apparatus and method for configuring a interconnect link between chiplets

A new peripheral component interconnect express (PCIe) link state can enhance power saving capabilities of a PCIe link operating in a flow control unit (FLIT) mode. A device can operate a data link with a host in a FLIT mode using fixed-sized packets, the data link being in a partial width link state (PLS) in which a first set of lanes of the data link are in an electrical idle state and a second set of lanes of the data link are in an active state available for data traffic with the host. The device can transition one or more lines of the second set of lanes from the PLS to a partial width standby link state (PSLS) in which the one or more lines of the second set of lanes are in a standby state that has lower power consumption than the active state.

Power management for peripheral component interconnect

Aspects relate to link speed for a peripheral component interconnect. In one aspect, an apparatus includes an interface circuit configured to provide an interface with a multiple lane data link, the data link having a first set of lanes in an active state and a second set of lanes in an idle state and a controller. The controller is configured to receive a request at the controller to change a data rate of the data link to a requested data rate, change the second set of lanes from an idle state to an active state, train the second set of lanes to the requested data rate, transfer data traffic from the first set of lanes to the second set of lanes after the training, and transmit the data traffic on the second set of lanes.

Growing community of inventors

Hyderabad Telangana, India

Ravi Kumar Sepuri