Lucent Technologies Inc.

International Business Machines Corporation

Agere Systems Inc.

Agere Systems Guardian Corp.

Ravi Kumar Kolagotla

Hosahalli R Srinivas

Jiancheng Mo

Mohit Kishore Prasad

Alexander Goldovsky

Santosh K Misra

Steven Frederick Oakland

Thomas Gregory Sopchak

Pamela Sue Gillis

Geoffrey Francis Burns

Jeanne Trinko-Mechler

Chris Joseph Rebeor

Maria Noack

Dennis A Miller

Thomas Baker

Jalil Fadavi-Ardekani

Christopher John Nicol

Richard Adam Cesari

Michael S Buonpane

Douglas J Rhodes

Feng Chen

Le Tieu Ly

William R Griesbach

Matthew Besz

Marck E Thierbach

An n-bit prefix tree adder includes n prefix trees, each associated with a bit position of the adder and including a number of computation stages. In accordance with an illustrative embodiment of the invention, the prefix trees are interconnected such that carry signals are computed at least partially in parallel. For example, a carry signal computed in an initial stage of a given prefix tree is used in subsequent stages of the given prefix tree without introducing substantial additional delay in computation of other carry signals in other prefix trees associated with higher bit positions. Carries computed for lower bit positions are thus used to compute carries for higher bit positions, but generate, propagate and/or transmit signals may be generated in an initial stage of each of the prefix trees without utilizing a primary carry input signal in the computation. The resulting adder architecture provides reduced logic depth, delay and circuit area relative to conventional architectures.

Prefix tree adder with efficient carry generation

A shared correlator system and method for a code division, multiple access (CDMA) receiver employs pipeline processing and information tags for sharing vector generation and correlation operations between processing units. A signal input to the CDMA receiver is provided as, for example, In-phase channel (I) and quadrature-phase channel (Q) sample vectors I and Q . Sample vectors I and Q are applied to the shared correlator of the CDMA receiver. Processing units request correlation operations by the shared correlator in which matched filter pseudo-noise (PN) vectors are correlated with the I and Q sample vectors I and Q . The shared correlator schedules correlation operations requested by processing units, generates matched-filter, PN vectors with associated identification tags for the correlation operations, and provides correlation results for the correlation operations. The shared correlator renders a shared task correlation system, and includes pipeline processing and identification tags to increase correlation bandwidth and facilitate result distribution to shared tasks.

Shared correlator system and method for direct-sequence CDMA demodulation

A first adder-subtracter combines the first input with the largest positive number capable of being represented by the number of bits in the datapath. A second adder-subtracter operating in parallel with the first adder-subtracter combines the first input with the largest negative number capable of being represented by the number of bits in the datapath. A third adder-subtracter combines the first, second, and third inputs and operates in parallel with the first and second adder-subtracters. A carry/sign detector circuit operating in parallel with all three adder-subtracters determines the sign and the carry of the sum of the second and third inputs. A MUX select logic circuit operates on the carry and the signs of the potential sums of all the adder-subtracters and the carry/sign detector and generates select signals for a multiple-input MUX which selects one of the potential sums or the largest positive or largest negative numbers as the final sum output of the multiple-input adder-subtracter with intermediate saturation.

Multiple-operand addition with intermediate saturation

A multiplier contains an array of partial product generators, at least one new modified-Booth encoder. Corresponding to each new modified-Booth encoder, the partial product generator array includes a new adder cell. The partial product generator array receives inputs Y,. . . YN with the Y,receiving partial product generator being a new partial product generator for generating a partial product PP*(0,j). The new modified-Booth encoder receives multiplier bits and a multiplicand input Y,, and generates control signals and a carry in signal. The new adder cell is connected to the new modified-Booth encoder, the Y,receiving new partial product generator and the (j&minus;2) row Y,receiving partial product generator and generates a partial product and an intermediate carry out signal so as to reduce the number of gate delay stages in the critical path of the multiplier.

Joint optimization of modified-booth encoder and partial product generator

A receiver for a spread spectrum communication system is disclosed in which a transmitter transmits a data signal to a receiver includes a memory for storing digital representation of the data signal received by the receiver. A memory input addressing unit defines a circulating data window. A first ring shift register circulates a first set of components of a spreading code. A second ring shift register circulates a second set of components of a spreading code. A selector selects one of the first set of components or the second set of components as selected components of the spreading code and an adder receives as inputs digital representations of the data signal from the circulating data window and the selected components of the spreading code. The adder provides an output that is the dot product of the inputs.

Digital communication system for high-speed complex correlation

A multiplier generates an array of partial products. The partial products are reduced in a converter having cells defining rows and columns. Cells adjacent to adders alternate between a cell that provides non-inverted outputs and a cell that provides inverted outputs, such that alternate rows of cells operate on non-inverted data and the intervening rows of cells operate on inverted data. A multiplexer for receiving the outputs from a row of cells may be an inverting multiplexer or a non-inverting multiplexer depending on the cell arrangement.

Efficient use of inverting cells in multiplier converter

In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing memory locations in a circular buffer. The address arithmetic unit includes a sign detector adapted to determine whether a sum of an address pointer and a precomputed comparison term is of a first state or a second state. A first adder adds an address pointer and a precomputed correction term to generate a first potential next address pointer. A second adder, operating in parallel with the first adder, adds the address pointer and a displacement to generate a second potential next address pointer. A selector adapted to select the first potential next address pointer as an output when the sign detector output and a sign bit of the displacement are different, and to select the second potential next address pointer as an output when the sign detector output and a sign bit of the displacement are the same.

Modulo address generator with precomputed comparison and correction terms

In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing a circular buffer. The address arithmetic unit includes a first selector adapted to receive as a first input a value representative of one greater than an ending address, a second input that is a beginning address, and a select input that is the sign of a displacement for stepping through addresses in a circular buffer. The first selector is adapted to select one of its inputs as an output. A carry-save adder adapted to receive as inputs an inverted representation of the first selector output, an address pointer, and a displacement. The carry-save adder is adapted to add the inputs to produce sum bits and carry bits as outputs. A sign detector adapted to determine whether a sum of the sum bits and carry bits is greater than or equal to zero, or less than zero, and for providing an output indicative of whether the sum is greater than or equal to zero, or less than zero. A second selector for receiving the comparator output and for selecting a component to include in a subsequent address pointer.

True modulo addressing generator

An unsigned integer comparator for use when comparing an n-bit received signal (such as an address) with an n-bit known signal ('comparison address'). The first stage of the comparator may be configured in advance, since the values of both a 'comparison signal' and a 'select signal' are known a priori. When the 'current signal' arrives, the bits of this signal are then compared against the associated bits of the comparison signal. Subsequent stages of the comparator perform comparison operations of increasing length, dependent upon the outcome of the previous stage (i.e., a first set of 2-bit comparisons, then 4-bit, 8-bit, etc.), until the entire n-bit integers are ultimately compared and a final output is generated.

Unsigned integer comparator

A flag generating circuit that uses a feedback mechanism to set or reset a flag associated with two systems with asynchronous clocks is provided. Upon receipt of a set flag (or reset flag) signal, the circuit immediately isolates the signal after setting (or resetting) the flag to prevent race conditions between the systems. The clock associated with the setting system is synchronously started when waiting to set the flag and synchronously stopped when waiting for the flag to be reset. The clock associated with the resetting system is synchronously started when waiting to reset the flag and synchronously stopped when waiting for the flag to be set. Accordingly, the flag generating circuit provides a race free and technology independent flag generating circuit capable of setting and resetting flags associated with asynchronous

Race free and technology independent flag generating circuitry

An integrated circuit includes an n-bit counter having a plurality of k subcounters where both n and k are integers. At least one of the subcounters includes a switchable device adapted to receive a carry-out signal from an adjacent subcounter as a first input, a test carry signal as a second input, and a control input, the switchable device being capable of providing one of its inputs as an output, the control input capable of controlling selection of the output which is a carry signal. The subcounter also includes an n/k-bit counter, the n/k-bit counter receiving the carry signal and providing n/k output bits, and logic for combining the n/k-bits output from the n/k bit counter with the carry-out signal from an adjacent subcounter to provide an output that is a carry-out signal from the subcounter. The logic introducing a single gate delay between the carry-out signal from the adjacent subcounter and the carry-out signal from the subcounter.

High-speed binary synchronous counter

A squarer generates an array of partial products. A method of squaring a representation of a number includes generating an array of partial products, combining the partial product on one side of a diagonal of the array with partial products on the other side of the diagonal to form a folded array of partial products, and combining each of at least one more than half of the partial products in the diagonal of the array with a corresponding one of the partial products in the folded array to produce a new folded array of partial products. In an alternative embodiment, the present invention is a circuit for squaring an n-bit representation of a number.

Squarer with diagonal row merged into folded partial product array

In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing memory locations in a circular buffer. The address arithmetic unit includes a first selector adapted to receive as a first input a value representative of one greater than an ending address, a second input that is a beginning address, and a select input that is the sign of a displacement for stepping through addresses in a circular buffer. The first selector is adapted to select one of its inputs as an output. A first adder combines an address pointer and displacement to produce a first potential next address pointer. A second adder combines the address pointer, the displacement, and a length modified by the sign of the displacement to produce a second potential next address pointer. A sign detector performs a comparison to determine whether a sum of the address pointer, displacement and a negative representation of the first selector output is greater than or equal to zero, or less than zero, and provides an output. A second selector selects one of the first potential next address pointer or the second potential next address pointer as the next address pointer based on the comparator output.

High speed module address generator

An integrated circuit including an adder that is a series of one-bit cascaded adder cells. The circuits that implement the adder cells are not all alike. The adder cells are of two types: an even adder cell and an odd adder cell. The even adder cells receive all inputs as noninverted inputs, provide as outputs a noninverted sum bit output and the inverse of the carry-out bit. The odd adder cells receive as inputs the inverse of the carry-in bit, all other inputs are noninverted, and provides as outputs a noninverted sum bit and a noninverted carry-out bit.

Adder with even/odd 1-bit adder cells

There is disclosed, a high speed comparator with bit-wise masking takes advantage of early availability of the reference word and mask word to generate conditional select signals, thereby minimizing the time required to generate a comparator output once the input word to be compared is available.

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Breinigsville, PA, United States of America

Ravi Kumar Kolagotla