International Business Machines Corporation

Motorola Corporation

Darpa

Ravi Kumar Arimilli

John Steven Dodson

Jerry Don Lewis

Guy L Guthrie

Lakshminarayana Baba Arimilli

Derek E Williams

James Stephen Fields, Jr

William John Starke

Jody B Joyner

Balaram Sinharoy

Leo James Clark

Satya Prakash Sharma

Sanjeev Ghai

Randal Craig Swanberg

Ramakrishnan Rajamony

Robert Alan Cargnoni

John Michael Kaiser

William Evan Speight

Robert Sidney Blackmore

Warren Edward Maule

Hanhong Xue

Chulho Kim

Piyush Chaudhary

Kenneth Lee Wright

Edward Joseph Seminaro

Vicente Enrique Chung

John Steve Dodson

Benjiman L Goodman

Claude Basso

Jean Louis Calvignac

Lixin Zhang

Timothy Michael Skergan

Bruce Gerard Mealey

Peter H Hochschild

Rama Krishna Govindaraju

Praveen S Reddy

Daniel Mark Dreps

Sudhir Dhawan

Michael Scott Allen

William Kurt Lewchuk

David W Siegel

Lakshminarayanan Baba Arimilli

Hugh Shen

James O Nicholson

Bernard Charles Drerup

Kevin Franklin Reick

Ronald Nick Kalla

Juan C Rubio

Michael Stephen Floyd

Gheorghe Calin Cascaval

Bradley David McCredie

George William Daly, Jr

Paul Umbarger

James Steven Fields, Jr

Michael J Ellsworth, Jr

Kevin Charles Gower

Frank David Ferraiolo

Francis Patrick O'Connell

Kevin Robert Covi

Bryan Ronald Hunt

Kirk Samuel Livingston

Keenan Wynn Franz

Thomas Michael Capasso

David Benjamin Shuler

John Michael Kaiser, Deceased

Guy Lynn Guthrie

Fabrice Jean Verplanken

Michael Steven Siegel

Colin Beaton Verrilli

Natarajan Vaidhyanathan

Donald W Plass

Chih-Jen Chang

Philippe Damon

Charles Francis Marino

Ronald Edward Fuhs

Robert J Reese

Hazim Shafi

Scott Michael Willenborg

Steven John Ahladas

Gerald J Fahr

Johnny James LeBlanc

Roger Ned Bailey

Daniel J Barus

John David McCalpin

Dennis G Gregoire

George A Lerom

Amy M Youngs

Lakshimarayana B Arimilli

John Michael Kaiser ()

Gerald Fahr

Daniel Barus

A memory lock mechanism within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory of the multiprocessor system. In response to a request for accessing the data block by a processing unit within the multiprocessor system, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the request for accessing the data block is denied. Otherwise, if the lock control section of the data block has not been set, the lock control section of the data block is set, and the request for accessing the data block is allowed.

Memory lock mechanism for a multiprocessor system

A system and computer program product are provided for controlling liquid-cooled electronics, which includes measuring a first set point temperature, T, wherein the Tis based on a dew point temperature, Tof a computer room. A second set point temperature, T, is measured, wherein the Tis based on a facility chilled liquid inlet temperature, T, and a rack power, P, of an electronics rack. A Modular Cooling Unit (MCU) set point temperature, T, is selected. The Tis the higher value of said Tand said T. Responsive to the selected T, a control valve is regulated. The control valve controls a flow of liquid that passes through a heat exchanger.

Environmental control of liquid cooled electronics

A technique for operating a high performance computing cluster includes monitoring workloads of multiple processors. The high performance computing cluster includes multiple nodes that each include two or more of the multiple processors. Workload information for the multiple processors is periodically updated in respective local job tables maintained in each of the multiple nodes. Based on the workload information in the respective local job tables, one or more threads are periodically moved to a different one of the multiple processors.

Techniques for dynamically assigning jobs to processors in a cluster using local job tables

A technique for operating a high performance computing (HPC) cluster includes monitoring communication between threads assigned to multiple processors included in the HPC cluster. The HPC cluster includes multiple nodes that each include two or more of the multiple processors. One or more of the threads are moved to a different one of the multiple processors based on the communication between the threads.

Techniques for dynamically assigning jobs to processors in a cluster based on inter-thread communications

A technique for performing cache injection includes monitoring, at a host fabric interface, snoop responses to an address on a bus. When the snoop responses indicate a data block associated with the address is in a shared state, input/output data associated with the address on the bus is directed to a cache that includes the data block in the shared state and is located physically closer to the host fabric interface than one or more other caches that include the data block associated with the address in the shared state.

Techniques for cache injection in a processor system based on a shared state

A technique for performing cache injection in a processor system includes monitoring, by a cache, addresses on a bus. Input/output data associated with an address of a data block stored in the cache is then requested from a remote node, via a network controller. Ownership of the input/output data is acquired by the cache when an address on the bus that is associated with the input/output data corresponds to the address of the data block stored in the cache.

Techniques for cache injection in a processor system from a remote node

A technique for performing cache injection includes monitoring addresses on a bus in response to a cache injection instruction. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block associated with the cache injection instruction.

Techniques for cache injection in a processor system using a cache injection instruction

A technique for performing cache injection includes monitoring addresses on a bus. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.

Techniques for cache injection in a processor system

A mechanism is provided for managing an input/output device communication request. A first operating system passes a call from a first application intended for an input/output device in a second data processing system to a first host fabric interface controller in the first data processing system without processing the call. The first host fabric interface processes the call to determine the second data processing system with which the call is associated. The first host fabric interface initiates a connection to a second host fabric interface in the second data processing system and transfers the call to a second operating system associated with the input/output device in the second data processing system via the connection to the second host fabric interface. The second operating system then processes the call intended for the input/output device without assistance from any application running on the second data processing system.

Management of application to I/O device communication requests between data processing systems

A mechanism is provided for managing a process-to-process inter-cluster communication request. A call from a first application is received in a first operating system in a first data processing system. The first operating system passes the call from the first operating system to a first host fabric interface controller in the first data processing system without processing the call. The first host fabric interface processes the call to determine a second data processing system in the plurality of data processing systems with which the call is associated, wherein the call is processed by the first host fabric interface without intervention by the first operating system. The first host fabric interface initiates an inter-cluster connection to a second host fabric interface in the second data processing. The call is then transferred to the second host fabric interface in the second data processing system via the inter-cluster connection.

Management of process-to-process inter-cluster communication requests

Disclosed are a method, a system and a computer program product for automatically allocating and de-allocating resources for jobs executed or processed by one or more supercomputer systems. In one or more embodiments, a supercomputing system can process multiple jobs with respective supercomputing resources. A global resource manager can automatically allocate additional resources to a first job and de-allocate resources from a second job. In one or more embodiments, the global resource manager can provide the de-allocated resources to the first job as additional supercomputing resources. In one or more embodiments, the first job can use the additional supercomputing resources to perform data analysis at a higher resolution, and the additional resources can compensate for an amount of time the higher resolution analysis would take using originally allocated supercomputing resources.

Event-based dynamic resource provisioning

A data processing system includes a system memory and a cache hierarchy that caches contents of the system memory. According to one method of data processing, a storage modifying operation having a cacheable target real memory address is received. A determination is made whether or not the storage modifying operation has an associated bypass indication. In response to determining that the storage modifying operation has an associated bypass indication, the cache hierarchy is bypassed, and an update indicated by the storage modifying operation is performed in the system memory. In response to determining that the storage modifying operation does not have an associated bypass indication, the update indicated by the storage modifying operation is performed in the cache hierarchy.

Data processing system and method for reducing cache pollution by write stream memory access patterns

A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model puts special purpose processing elements on the same playing field as processors, from a programming perspective, operating system perspective, and power perspective. The operating system can get work to a security engine, for example, in the same way it does to a processor.

Binding a process to a special purpose processing element having characteristics of a processor

A data processing system includes a system memory, one or more processing cores, and a memory controller that controls access to a system memory. The memory controller includes a memory speculation mechanism that stores historical information regarding prior memory accesses. In response to a memory access request, the memory controller speculatively initiates access to the system memory based upon the historical information in the memory speculation mechanism in advance of receipt of a coherency message indicating that the memory access request is to be serviced by reference to the system memory.

Method and system for thread-based memory speculation in a memory subsystem of a data processing system

A system and method are provided for performing setup operations for receiving a different amount of data while processors are performing message passing interface (MPI) tasks. Mechanisms for adjusting the balance of processing workloads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. An MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, setup operations may be performed while processors are performing MPI tasks to prepare for receiving different sized portions of data in a subsequent computation cycle based on the history.

Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks

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Austin, TX, United States of America

Ravi Kumar Arimilli