Intel Corporation

Other

Analog Devices,inc.

Ravi Kolagotla

Charles P Roth

Ravi P Singh

Bradley C Aldrich

David B Witt

Juan Guillermo Revilla

Jose Fridman

Ramesh V Peri

Raghavan Sudhakar

John Fernando

Ravishankar Iyer

Blaise B Fanning

Ioannis T Schoinas

Daniel Cutter

Nitin V Sarangdhar

Michael J Allen

Lawrence A Booth

William C Anderson

Marc M Hoffman

Jose Niell

Ramadass Nagarajan

Raul N Gutierrez

Ryo Inoue

Quang T Le

Hebbalalu S Ramagopal

Moinul Syed

Srinivas P Doddapaneni

Tien Dinh

Russell L Rivin

Ioannis Yannis T Schoinas

Tien Dingh

Michael Allen

Embodiments are directed to managing access to input/output devices by virtual machines (VMs). A first VM and a second VM are implemented. An I/O device controller driver has a first driver portion in the first VM and a second driver portion in the second VM. The first driver portion includes a configuration engine to configure the I/O device controller with I/O device-VM mappings, where a first I/O device is mapped exclusively to the first VM, and a second I/O device is mapped to at least the second VM. The second VM includes a general processing engine to call for I/O devices via the second driver portion, and in response to a call by the general processing engine for access to the first I/O device the second driver portion is to send an access request to the first driver portion.

Versatile protected input/output device access and isolated servicing for virtual machines

In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

Method, apparatus, system for representing, specifying and using deadlines

In a modified Harvard architecture, conventionally, read operations in the same cycle are only implemented when different memory banks are to be accessed by the different read operation. However, when different sublines in the same memory bank are being accessed, cycles may be saved by accessing both sublines in the same cycle.

Accessing data from different memory locations in the same cycle

Apparatus, system, and method for scalable traceback techniques for channel decoding are described.

Scalable traceback technique for channel decoder

A memory addressing technique using load buffers to improve data access performance. More particularly, embodiments of the invention relate to a method and apparatus to improve cache access performance in a computer system by exploiting addressing mode information within an instruction accessing a cache memory or other memory device within the computer system.

Virtualized load buffers

A processor may include a local addressable memory, e.g., an SRAM, in parallel with a local cache at the highest level of the memory hierarchy, e.g., Level 1 (L1) memory. A local memory controller may handle accesses to L1 memory. The local memory controller may determine the page which includes the requested memory location and examine a page descriptor, e.g., an L1 SRAM bit, to determine if the page is in local memory. The local memory controller routes the access to the local addressable memory or the local cache depending on the state of the L1 SRAM bit.

Method for extending the local memory address space of a processor

In one embodiment, an integrated circuit provides a test access port that communicates with scan chain registers in a processor core. The integrated circuit synchronizes data transferred between a debug controller that operates under control of a test clock (TCK) and the processor core that operates under control of a processor clock (CLK).

Data synchronization for a test access port

A register file architecture in a general purpose digital signal processor (DSP) supports alignment independent SIMD (Single Instruction/Multiple Data) operations. The register file architecture includes a register pair and an alignment multiplexer. Two 32 bit grouped words may be loaded into the register pair. Each grouped word includes four 8 bit operands. The alignment state of the 32 bit words may be determined by the two least significant bits (LSBs) of the pointer addresses of the grouped words. These LSBs are used to control the alignment MUX to select n operands from the two 32 bit grouped words and output an aligned 32 bit grouped word to execution units for parallel processing.

General purpose register file architecture for aligned simd

In one embodiment, techniques are disclosed for causing a programmable processor to process one instruction at a time. Single-step debugging may be performed by taking an exception after each instruction or by invoking emulation mode after each instruction. The particular single-step debugging technique may be based upon state of control bits, or may be based upon the processor's current mode of operation, or both.

Single-step processing and selecting debugging modes

In one embodiment, a programmable processor searches an array of N data elements in response to N/M machine instructions, where the processor has a pipeline configured to process M data elements in parallel. In response to the machine instructions, a control unit directs the pipeline to retrieve M data elements from the array of elements in a single fetch cycle, concurrently compare the data elements to M current extreme values, and update the current extreme values, as well as M references to the current extreme values, based on the comparisons.

Maintaining even and odd array pointers to extreme values by searching and comparing multiple elements concurrently where a pointer is adjusted after processing to account for a number of pipeline stages

In one embodiment, a digital-signal processor (DSP) is described for multi-level global accumulation. The DSP includes a plurality of absolute difference determinators in a first stage. The absolute difference determinators may include arithmetic logic-units (ALUS) in combination with multiplexers. By using multiple absolute difference determinators, the throughput of the DSP is increased. An existing multiplier may be reconfigured into an adder tree to process the absolute difference results obtained in the first stage. To further increase, throughput, multiple DSPs with multiple absolute difference determinators may be operated in parallel.

DSP unit for multi-level global accumulation

In one embodiment, a method is disclosed for holding instruction fetch requests of a processor in an extended reset. Fetch requests are disabled when the processor undergoes a reset. When the reset is completed, fetch requests remain disabled when the instruction memory is being loaded. When loading of the instruction memory is completed, fetch requests are enabled.

Processor reset and instruction fetches

In an embodiment, a system may include a processor that handles a number of events. These events may include general purpose interrupts (GPIs) assigned to particular devices in the system. Addresses for event service routines appropriate for particular events may be stored in an event vector table (EVT). In a system with a number of devices that utilize the processor's resources, some interrupts may be overloaded, that is, assigned to more than one device. If an overloaded interrupt occurs, the processor may override the EVT entry and select an address supplied by a system controller at a set of reset vector pins.

Event vector table override

In one embodiment, a modulo addressing unit for a processor is described that includes a plurality of adders to generate an uncorrected target module address and at least one corrected target module address in parallel. A comparator selects one of the target module addresses a function of a base address (b) for a circular buffer, a length (L) of the circular buffer, an index address (I) and a modifier value (M). In one embodiment the comparator selects a first corrected target module address when I&plus;M<B, a second corrected target module address when I&plus;M>&equals;B&plus;L and an uncorrected module address when B<&equals;I&plus;M<B&plus;L.

Modulo addressing

In one embodiment, a digital signal processor (DSP) is described for multi-level global accumulation. The DSP includes a plurality of absolute difference determinators in a first stage. The absolute difference determinators may include arithmetic logic units (ALUs) in combination with multiplexers. By using multiple absolute difference determinators, the throughput of the DSP is increased. An existing multiplier may be reconfigured into an adder tree to process the absolute difference results obtained in the first stage. To further increase throughput, multiple DSPs with multiple absolute difference determinators may be operated in parallel.

Growing community of inventors

Austin, TX, United States of America

Ravi Kolagotla