Cirrus Logic Inc.

Silicon Laboratories Inc.

Analog Devices,inc.

Texas Instruments Corporation

Ravi Kishore Kummaraguntla

Axel Thomsen

John L Melanson

Aslamali A Rafi

Christian Larsen

John Christopher Tucker

Michael Ray Elliott

Stephen Timothy Hodapp

Scott Gregory Bardsley

Paul Wilson

Christophe J Amadi

Kathryn Rose Holland

Arashk Norouzpourshirazi

Eric Jerome King

Timothy Joseph Dupuis

Ahmed Mohamed Abdelatty Ali

Ramin Zanbaghi

Abdulkerim Coban

Graeme G Mackay

John Gregory Harris

Michael G Khazhinsky

Zhiliang Julian Chen

Ruifeng Sun

Carroll Clifton Speir

Yongjie Cheng

James C Camp

Bryan Scott Puckett

Vivek Saraf

Wei Xu

Mujo Kozak

Bo-Ren Wang

Dhrubajyoti Dutta

A system may include a sampling capacitor and a switch network. The switch network may include one or more first sampling switches electrically coupled to the sampling capacitor and configured to be activated during a first phase of a sampling cycle of the system and one or more second sampling switches electrically coupled to the sampling capacitor and configured to be activated during a second phase of the sampling cycle, wherein the switch network is configured to reset the sampling capacitor to a data-independent and/or signal-independent charge during a reset phase of the sampling cycle.

Data-dependent glitch and inter-symbol interference minimization in switched-capacitor circuits

A system may include a switched-capacitor analog front end comprising a plurality of switches for sampling an analog physical quantity and a bootstrap generation network electrically coupled to the plurality of switches and configured to generate a bootstrap sampling clock for controlling the plurality of switches and generate a floating supply voltage for the bootstrap sampling clock based on the analog physical quantity.

Beyond-the-rails switched-capacitor floating front end with over-voltage protection

An apparatus may include a sense resistor comprising a plurality of parallel-coupled resistor elements, a plurality of positive voltage sense points, and a plurality of negative voltage sense points. A first passive combination network may be configured to combine the plurality of positive voltage sense points into a single positive sense terminal and a second passive combination network may be configured to combine the plurality of negative voltage sense points into a single negative sense terminal. The first passive combination network and the second passive combination network may be arranged such that a sense voltage is measurable between the single positive sense terminal and the single negative sense terminal and a dependence of the sense voltage on a variation in current density in the parallel-coupled resistor elements is minimized.

Sense resistor and method for forming same

A signal processing system may include a signal path and a chop management circuit. The signal path may comprise a chopper configured to chop a differential input signal to the signal path at a chopping frequency and a low-pass filter downstream of the chopper and configured to filter out intermodulation products of a direct current offset of the signal path and intermodulation products of an aggressor on the differential input signal in order to generate an output signal. The chop management circuit may be communicatively coupled to the chopper and configured to, based on operational parameters associated with the signal path, dynamically manage energy of one or more clock signals used to define the chopping frequency.

Chop tone management for a current sensor or a voltage sensor

The present disclosure relates to circuitry for determining a temperature coefficient value of a resistor. The circuitry comprises circuitry for supplying an AC current signal to the resistor, circuitry for measuring a first voltage across the resistor when the AC current signal is supplied; and processing circuitry configured to determine the temperature coefficient value based on the first voltage.

Determining a temperature coefficient value of a resistor

A system may include a front end differential amplifier having two input terminals, two input resistors, each of the two input resistors coupled to a respective one of the two input terminals, and an input common mode biasing circuit for an output stage of the front end differential amplifier, the input common mode biasing circuit comprising two current sources configured to generate currents for biasing the output stage of the front end differential amplifier.

Current sensing circuitry

Input impedance biasing may be improved with an ultra-high-input-impedance biasing circuit having low temperature variation. The impedance biasing circuit may include a first transistor coupled to a first power supply and a second transistor coupled to a second power supply. A gate of the first transistor may be coupled to a gate of the second transistor at an intermediate bias node. The first transistor and the second transistor may provide a selected DC impedance at the intermediate bias node. The impedance may be used to provide low-pass and or high-pass filtering of audio signals and/or noise.

Input impedance biasing

In one form, a radio frequency (RF) transmitter includes an RF signal source, a balanced/unbalanced transformer (balun), and first and second amplification circuits. The balun has a primary side adapted to be coupled to an antenna, and a secondary side. The first amplification circuit has an input coupled to the RF signal source, and an output coupled to the primary side of the balun. The second amplification circuit has an input coupled to the RF signal source, and an output coupled to the secondary side of the balun. The second amplification circuit has a higher output power than the first amplification circuit.

Multiple power transmitter for RF receiver or the like

A balun includes an input coil and an output coil with first and second outputs that vary during normal operation. The output coil has a center point connection that remains substantially constant during normal operation. An ESD circuit provides a low impedance path between the center point connection and chip ground when the voltage at the center point connection is above a first threshold voltage or below a second threshold voltage and isolates the center point connection from chip ground otherwise. Another ESD protection circuit provides ESD protection for other input or output terminals of the integrated circuit by selectively coupling the other input or output terminals to chip ground. Thus, a charge that builds up between one of the balun outputs and another terminal on the integrated circuit can be safely dissipated.

Electrostatic discharge protection for a transformer balun

A die is mounted in an integrated circuit package. The die includes a balun circuit and an electrostatic discharge (ESD) circuit coupled to a ground of the integrated circuit die. The package has a first output pin coupled to a first terminal of the balun and has a second output pin coupled to a second terminal of the balun through first and second bond wires. The second output pin is connected to board ground. A third bond wire is disposed between the second package terminal and the ESD circuit to provide a safe discharge path through the third bond wire for ESD events affecting the first and second output terminals. Thus, a charge that builds up involving one of the output terminals coupled to the balun can be safely dissipated.

Electrostatic discharge protection for a balun

A transceiver includes a transmit/receive terminal, a receiver input terminal, a plurality of impedance transformation networks coupled in series, a plurality of power amplifiers, and a controller. Each impedance transformation network has first and second ports. The impedance transformation networks include at least one selectable impedance transformation network having a resonant mode and a termination mode. The power amplifiers have outputs respectively coupled to the second ports of corresponding ones of the impedance transformation networks. In a receive mode, the controller selects the resonant mode for each selectable impedance transformation network and disables all power amplifiers. In a transmit mode, the controller enables a selected power amplifier and selects the resonant mode of any upstream selectable impedance transformation network, and selects the termination mode of a downstream selectable impedance transformation network.

Transceiver suitable for multiple power level operation and method therefor

A transceiver comprises a transmit/receive terminal, a receiver input terminal, a scalable impedance network, a plurality of power amplifiers, and a receiver. The scalable impedance network is coupled between the transmit/receive terminal and the receiver input terminal and has a plurality of taps in an order between the transmit/receive terminal and the receiver input terminal, in which an impedance looking into any given tap toward the transmit/receive terminal is smaller than an impedance looking into a subsequent tap toward the transmit/receive terminal, if any, in the order. The plurality of power amplifiers are arranged in an order and have outputs respectively coupled to the plurality of taps of the scalable impedance network. A power of any given power amplifier is higher than a power of a subsequent power amplifier, if any, in the order. The receiver is coupled to the receiver input terminal.

A ring oscillator that is more insensitive to power supply ripple utilizes an amplifier circuit having a first input coupled to a reference voltage. A current is generated that represents a control voltage supplied to the oscillator control circuit. That current is mirrored and supplied as a control current to the oscillator. An amplifier is used in a feedback loop to ensure that incremental variations in source to drain voltage of a first transistor of the current mirror is present in a second transistor of the current mirror to make the control current more immune to supply ripple.

VCO insensitive to power supply ripple

Techniques are disclosed relating to radio frequency (RF) power detection. In one embodiment, a power detection unit is disclosed that includes a multiplier circuit configured to receive a first voltage of a voltage differential signal at gates of a first transistor pair and a second voltage of the voltage differential signal at gates of a second transistor pair. The first multiplier is configured to output a current that varies proportionally to a square of a voltage difference between the first and second voltages. In some embodiments, sources of the first transistor pair are coupled to sources of the second transistor pair, and the sources of the second transistor pair are coupled together. In some embodiments, the power detection unit is configured to compensate for mismatched transistors by applying offset voltages to bodies of transistors in the first and second transistor pairs.

Accuracy power detection unit

Clock processors are provided to economically control system and data clocks in high-speed signal converters. The processors generally include at least one of a delay-locked loop, phase-locked loop or a duty cycle stabilizer which generates an error signal in its operation. In the example of a stabilizer, it is configured to respond to an input clock to initiate a first portion of each cycle of the system clock and to include a control loop to provide an error signal that controls a second portion of the cycle to thereby maintain a selected duty cycle. The processors also include a data clock aligner configured to share the error signal and provide a data clock that is delayed by a selected delay from a selected one of the input and system clocks. In addition to providing effective control that is independent of disturbing effects (e.g., temperature and clock rate), the shared use reduces processor costs.

Growing community of inventors

Jamestown, NC, United States of America

Ravi Kishore Kummaraguntla