Freescale Semiconductor,inc.

Ravi Gupta

Ravindraraj Ramaraju

David R Bearden

Arvind Raman

Robert Bailey

An array of memory bit cells are operable to provide a memory device having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array can thus be used for conventional memory storage operations, and also for operations, such as matrix operations, that provide for the alteration of the arrangement of stored data elements.

Memory device having shifting capability and method thereof

A processor-implemented method for making a semiconductor device having a test logic block and a functional logic block is provided. The method includes retrieving hardware description for at least one test logic block and mapping the hardware description for the at least one test logic block to logic gates to generate at least one synthesized test logic block. The method further comprises retrieving hardware description for at least one functional logic block and mapping the hardware description for the at least one functional logic block to logic gates to generate at least one synthesized functional logic block. The method further includes merging the at least one synthesized test logic block with the at least one synthesized functional logic block when the at least one functional logic block meets at least one criterion for selection as a candidate for merger with the at least one test logic block.

Method and apparatus for making a semiconductor device using hardware description having merged functional and test logic blocks

A memory device includes a latch component including a first input configured to receive a functional data bit associated with a functional operation, a second input configured to receive a memory test/repair data bit associated with a memory test operation, and a latch comprising a data input and a data output and select logic configured to selectively connect one of the first input or the second input to the data input of the latch based on a mode of operation of the memory device. A method includes operating a memory device in a first mode associated with a memory test operation and in a second mode associated with a functional operation. The method further includes storing a memory test/repair data bit at a latch component of the memory device in the first mode and storing a functional data bit at the latch component in the second mode.

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Austin, TX, United States of America

Ravi Gupta