Qualcomm Incorporated

Avago Technologies General IP (singapore) Pte. Ltd.

Ravi Gupta

Ali Afsahi

Hongrui Wang

Arun Gothekar

Gur Prasad Srivastava

Nileena Pathalayi Alakandy

Choong Yul Cha

Bhavya Soneta

Mukesh Kumar Pravinbhai Savaliya

Rajesh Chava

A peripheral controller includes a serial engine configured to provide an interface to a serial bus, a multiplexer configured to select between transactions directed to the serial bus and initiated in a plurality of execution environments, and an access control circuit configured to determine when a first transaction to be executed over the serial bus is initiated from a first execution environment, enforce an access policy when the first execution environment is a secured execution environment, determine when a second transaction is initiated from a second execution environment, block the second execution environment and a peripheral device from accessing the serial bus when the first execution environment is accessing the serial bus, and provide the second execution environment and the peripheral device access to the serial bus when the second execution environment is an unsecured execution environment. The access policy may be based on an address of a peripheral device.

Sharing and protecting secured subordinate devices on an unsecured bus

A broadband digital transmitter is disclosed. The digital transmitter includes a vector decomposer circuit, a phase selector circuit, and a digital power amplifier (DPA). The vector decomposer circuit receives baseband in-phase (I) and quadrature (Q) signals and decomposes the baseband I and Q signals into an offset envelope signal and a non-offset envelope signal. The phase selector circuit receives a plurality of phase offset local oscillator (LO) signals and outputs, responsive to the baseband I and Q signals, offset LO signals and non-offset LO signals. The DPA processes the offset envelope signal, the non-offset envelope signal, the offset LO signals, and the non-offset LO signals to generate an output signal of the digital transmitter.

Broadband digital transmitter using &#x3c0;/4 phase offset local oscillator (LO) signals

A DC voltage offset correction circuit that provides for correction of a DC offset voltage of an output of a filter stage of a complex filter circuit includes a DC offset sensing device that is connected to an output of a filter stage of a complex filter to generate an offset presence signal indicating presence of the DC offset voltage at the output of the filter stage. The digital-to-analog converter applies a compensation signal to the output conditional on the offset presence signal. A programming register receives the offset presence signal to perform a binary search to generate a digital signal to force the digital-to-analog converter to apply the compensation voltage to the output of the filter stage. A filter controller sets the compensation voltage level in the programming register to match a programmed gain value of the filter stage.

DC offset correction for high gain complex filter

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Sunnyvale, CA, United States of America

Ravi Gupta