Lsi Logic Corporation

Ravi Bhaskaran

Advait Madhav Mogre

Christopher R Keate

Dojun Rhee

Daniel A Luthi

Dariush Dabiri

Kedar Shirali

Ting-Yin Chen

An inexpensive synchronous detection module is disclosed for a sideband signal receiver that provides for flexibility in design of the tuner. The detection module is adaptable to detection of upper or lower sideband signals. One embodiment includes an analog-to-digital converter, a Hilbert transform filter, a sideband selection switch, a complex multiplier, a carrier recovery. loop, a matched filter, and a decimator. The analog-to-digital converter oversamples an intermediate frequency (IF) signal from the tuner, and the Hilbert transform filter generates a Hilbert transform of the digital IF signal. An analytic IF signal can be generated from the digital IF signal by multiplying the Hilbert transform of the digital IF signal by j(&equals;sqrt(&minus;1)), and adding the resulting imaginary-valued signal to the digital IF signal. The sideband selection switch can &ldquo;flip&rdquo; the analytic IF signal by inverting the imaginary-valued signal. The complex multiplier multiplies the analytic IF signal by a complex-value sinusoid to shift the analytic IF signal to baseband. The resulting analytic baseband signal is match filtered and decimated to form a baseband double sideband signal with one sample per symbol period. The carrier recovery loop operates on the imaginary part of the analytic baseband signal to generate the complex sinusoid that shifts the analytic IF signal to baseband.

Method and apparatus for pilot-aided carrier acquisition of vestigial sideband signal

Digital interference rejection of a signal is accomplished by first converting the signal to digital. Then a second signal is generated and mixed with the first signal. This combined signal is then filtered. The signal can then be scaled as needed, resulting in a finely tuned, interference free signal.

Method and apparatus for digital interference rejection

A communications receiver system is presented for detecting burst errors and providing erasure information to a block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, the receiver includes a demodulator which includes circuitry to detect error bursts in the received symbol sequence. Once detected, the locations of symbols in error are marked in the form of erasure flags. An error correction decoder is then able to correct up to twice as many errors with the additional information provided by the erasure flags.

Non-equalized digital receiver using block decoding with erasure and

A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.

Digital receiver using a concatenated decoder with error and erasure

A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder (outer decoder), thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.

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Santa Clara, CA, United States of America

Ravi Bhaskaran