Motorola Corporation

Motorola Solutions, Inc.

Freescale Semiconductor,inc.

Raul Salvi

Keith Andrew Tilley

Enrique Ferrer

Gustavo Dario Leizerovich

Joseph P Heck

Cesar W Carralero

Geetha B Nagaraj

Charles R Ruelke

Armando J Gonzalez

David J Graham

Dane E Blackburn

John D Wetters

Steven P Hoggarth

Ramon Ponce

Branko L Avanic

Nicholas Giovanni Cafaro

Darrell Eugene Davis

Wayne M Phang

Peter J Yeh

John J Parkes, Jr

Rodger W Caruthers

Shafiullah Syed

Jerry T Bolton, Jr

Edward A Diaz

James J Riches

Pedro Julio Landin

Atif A Meraj

Christopher Calvo

James C Goatley

Thomas R Harrington

Systems and methods for processing radiofrequency signals using modulation duty cycle scaling. One system includes a first receive path configured to directly sample a first signal in a first frequency range. The system includes a second receive path configured to convert a second signal in a second frequency range. The second receive path includes a receive modulator operating over a duty cycle. The receive modulator is configured to adjust the duty cycle by a predetermined scaling factor.

System and method for processing radiofrequency signals using modulation duty cycle scaling

A tunable multi-path filter, a method for filtering a radio frequency signal with the tunable multi-path filter, and a communication device including the tunable multi-path filter. In one embodiment, the tunable multi-path filter includes a voltage controlled current source, an oscillator source, and at least two filter paths. The voltage controlled current source for receiving a radio frequency (RF) signal and generating a current signal. The oscillator source for generating a tunable clock signal. Each of the at least two filter paths are coupled to the voltage controlled current source and the oscillator source, and are configured to generate an output voltage signal based at least in part on the current signal and the tunable clock signal. In some embodiments, the tunable multi-path filter further includes a carrier signal rejection component that is configured to reduce the carrier feedthrough in the output voltage signals.

Tunable multi-path filter

Disclosed herein are systems for and methods of using a mirrored wideband baseband current for automatic gain control of an RF receiver. In an embodiment, a system includes an RF receiver having an adjustable gain and being configured to direct convert a received wideband RF signal to a wideband baseband current signal. The system further includes a current replicator coupled to the receiver and configured to generate a mirrored current of the wideband baseband current signal. The system further includes a wideband signal-level detector configured to receive the mirrored current from the current replicator, and to measure and output a signal-level value of the mirrored current. The system further includes an automatic gain-control circuit configured to receive the signal-level value from the wideband signal-level detector, and to adjust the gain of the receiver based at least in part on the received signal-level value.

Systems for and methods of using a mirrored wideband baseband current for automatic gain control of an RF receiver

Disclosed herein are embodiments of an active RC filter that has a gain-setting attenuator. An embodiment takes the form of a filter circuit having a filter-circuit input node; a filter-circuit output node; an operational amplifier (op-amp) having first and second inputs and also having an output coupled to the filter-circuit output node; and a passive feedback path extending between the filter-circuit output node and the first op-amp input, the passive feedback path having a gain-setting attenuator segment in series with a signal-filtering segment.

Active RC filter having gain-setting attenuator

A method for tuning a filter is provided. The amplitude of a first signal (I) is compared with the amplitude of a comparison signal. The first signal is generated with a first filter, which receives a first input signal, and there is a phase difference between the first signal (I) and the comparison signal. A tuning signal is then generated based on differences between the amplitudes of the first signal (I) and the comparison signal. The tuning signal compensates for any phase and/or amplitude offset in the first signal (I).

Broadband input frequency adaptive technique for filter tuning and quadrature generation

A method for minimizing undesired signal coupling from digital interface between peripherals is presented. The method includes transmitting over the interface first and second signals having a parameter &#x3b6;set by a dynamic sequencer respectively to a first and second value &#x3b1;and &#x3b1;, receiving the first and second signal and generating a first and second interference metric respectively for the first and second signal. The first and second interference metrics are correlated to generate a final parameter value &#x3b1;, and a transmitter is then configured to transmit a third signal over the interface with the final parameter value &#x3b1;.

High speed minimal interference adaptive tranceiver interface and method thereof

A frequency synthesizer that utilizes locked loop circuitry, for example delay locked loop and/or phase locked loop circuits is provided with a means for minimizing static phase/delay errors. An auto-tuning circuit and technique provide a measurement of static phase error by integrating the static phase error in the DLL/PLL circuit. A correction value is determined and applied as a current at the charge pump or as a time/phase offset at the phase detector to minimize static phase error. During normal operation the DLL/PLL is operated with the correction value resulting in substantially reduced spur levels and/or improved settling time.

Method and apparatus for correcting phase offset errors in a communication device

A method and an apparatus () for generating corrected quadrature phase signal pairs in a communication device are provided. The apparatus () includes a quadrature phase generator (), programmable delay elements () and a control circuit (). The programmable delay elements () receive a quadrature phase signal pair (signals Iand Q) from the quadrature phase generator (). The control circuit () generates a control signal () based on outputs () of the programmable delay elements (). The control signal () configures the programmable delay elements (). The programmable delay elements () are configured to adjust delay between the signals I () and Q (). The programmable delay elements () are also used to adjust duty cycle for the quadrature phase signal pair to provide the corrected quadrature phase signal pair.

Method and apparatus for generating corrected quadrature phase signal pairs in a communication device

A signal generation power management control system () for use in a portable communications device includes a digital signal processor (DSP) () for processing a digital source input and providing a digital processed bit stream A digital-to-analog converter (DAC) () is used for converting the digital processed bit stream to provide an analog signal. A power management controller () within the DSP () is then used for interpreting control parameters of signal processing components used within the portable communications device and dynamically adjusting the bias current of these components based on minimal signal requirements of the analog signal.

Signal generation power management control system for portable communications device and method of using same

A method and apparatus for improving signal reception in a receiver () by performing all-channel and/or on-channel estimations on a received signal so as to predict future RF environments. The prediction is achieved through the use of one or more detector systems () positioned to sample and detect predetermined signal metrics of the received signal () prior to analog-to-digital conversion () and subsequent post-processing (). Future estimations of the channel condition are thus generated prior to the arrival of the actual samples () at a controller section (). The detectors () provide triggers () to the controller () so that active stages () within the receiver () can be adjusted and scaled as needed via a serial port interface (SPI) () based on signal conditions.

Method and apparatus for improving signal reception in a receiver

A linear power efficient radio frequency (RF) driver system () includes a pre-driver amplifier () for amplifying an RF signal; and an output driver () having a substantially high impedance input for amplifying the signal from the pre-driver amplifier (). A bias controller () is used for controlling the RF power output of the output driver () where the current drain of the pre-driver amplifier () and the bias controller () are controlled to a minimum level while maintaining linearity of the output driver (). The system and method of the invention work to provide minimal current drain in portable products using simultaneous current and power amplifier reduction based on driver input swing to lower signal distortion.

Linear power efficient radio frequency (RF) driver system and method with power level control

An adaptive analog-to-digital converter (ADC) system () includes an automatic gain control (AGC) controller () for receiving both in-band and out-of-band signals from a radio frequency (RF) receiver and producing an AGC control signal therefrom. A digital signal processor (DSP) () is then used for interpreting the AGC control signal and providing an adjustment signal to an ADC (). The ADC () uses the adjustment signal to dynamically control efficiency of the ADC systemby adjusting bit resolution, reference capacitance and bias based upon the RF signal received and desired protocol requirements presented to the AGC controller ().

Signaling dependent adaptive analog-to-digital converter (ADC) system and method of using same

A prescaler ( ) includes a frequency divider ( ) having an input node ( ) and a divider output ( ). The frequency divider is coupled to a clock signal and has a predetermined divisor. Series-coupled delay elements ( ) are coupled to the divider output and to the clock signal. Each delay element includes a delayed output ( ) and adds a delay equal to the clock period at the delayed output. The prescaler also includes transmission gates ( ), each transmission gate coupled between the input node and the delayed output of a corresponding one of the delay elements. When one of the transmission gates is enabled and couples the delayed output of an nth one of the delay elements to the input node, the divider output frequency equals the clock frequency divided by the predetermined divisor plus n.

Prescaler method and apparatus

A sigma-delta DAC circuit includes a sigma-delta modulator for producing and outputting an n-bit digital signal representative of an input analog signal, wherein n is a positive integer greater than 1, and is preferably equal to 4, 5 or 6. A differential n-bit DAC is for converting a 2 -bit digital signal and a 2 -bit inverted digital signal processed and output by a bit shifter and a differential decoder to a differential analog signal. The sigma-delta modulator has a movable zero for enabling dynamic spectral shaping of the differential analog signal.

Differential sigma-delta DAC with dynamic spectral shaping

A fast attack Automatic Gain Control (AGC) loop ( ) having the capability to selectably shape one or more decaying current sources ( ) contained within an off-channel feedback loop and an on-channel feedback loop of the AGC loop by sequentially and selectively switching out weighted transistors (Tr , Tr , Tr , . . . , Tr ) of a plurality of weighted current mirrors ( ) at predetermined intervals (t , t , t , . . . , t ).

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Boca Raton, FL, United States of America

Raul Salvi