Intel Corporation

Raul N Gutierrez

Balaji Vembu

Daniel Nemiroff

Karthi R Vadivelu

Suryaprasad Kareenahalli

Nitin V Sarangdhar

Zohar Bogin

Mikal Hunsaker

Randy B Osborne

Huimin Chen

Steven Bernard McGowan

Joseph A Bennett

Darren L Abramson

Abdul Rahman Ismail

Abhishek Singhal

Reuven Rozic

Ravi Kolagotla

Hemant G Rotithor

Khee Wooi Lee

Kah Meng Yeem

Buderya S Acharya

Surya Kareenahalli

Ioannis Yannis T Schoinas

Embodiments of the present disclosure are directed toward a universal serial bus (USB) device and a USB host controller. The USB device and USB host controller may be configured to couple to one another via a USB link that may include a high-speed data line and a low-speed data line. The USB device may then transmit, via the high-speed data line, an indication of a digital image to the USB host controller. Other embodiments may be described and/or claimed.

High bandwidth universal serial bus (USB) camera

An example includes an apparatus for transmitting Universal Serial Bus (USB) packets. The apparatus includes a transmitter adapter to receive a USB packet from a USB device. The transmitter adapter can further generate one or more alternate mode packets based on the USB packet. The transmitter adapter can also transmit the alternate mode packets via an alternate mode connection.

Transmitting universal serial bus (USB) data over alternate mode connection

An apparatus is described herein. The apparatus includes a Universal Serial Bus (USB) component and a controller interface. The controller interface is to allocate register space for interfacing with the USB component and the USB component is virtualized into multiple instantiations. The apparatus also includes a secure environment, and the secure environment further virtualizes the multiple instantiations such that the multiple instantiations are owned by the secure environment.

Additional secured execution environment with SR-IOV and xHCI-IOV

In one embodiment an electronic device includes a processor and at least one universal serial bus (USB) subsystem comprising logic, at least partially including hardware logic, configured to detect a connection from a remote electronic device to a USB port of the electronic device, determine whether the USB port of the electronic device is to act as an upstream facing port or a downstream facing port, and in response to a determination that the USB port of the electronic device is to be configured as an upstream facing port, to implement a port mapping process to map the USB port to one of a device controller or a debug controller. Other embodiments may be described.

System and method for universal serial bus (USB) protocol debugging

Systems and techniques for privacy protected input-output port control are described herein. In an example, an indication may be obtained that a protected port is disabled. A set of application attributes stored in a secure memory location may be compared to a set of attested application attributes to create a verification flag. At least one port attribute of the protected port may be obtained based on the verification flag. The protected port may be enabled using the at least one port attribute. Other examples, for controlling an input-output port using computer firmware and trusted execution techniques are further disclosed.

Privacy protected input-output port control

Embodiments are directed to managing access to input/output devices by virtual machines (VMs). A first VM and a second VM are implemented. An I/O device controller driver has a first driver portion in the first VM and a second driver portion in the second VM. The first driver portion includes a configuration engine to configure the I/O device controller with I/O device-VM mappings, where a first I/O device is mapped exclusively to the first VM, and a second I/O device is mapped to at least the second VM. The second VM includes a general processing engine to call for I/O devices via the second driver portion, and in response to a call by the general processing engine for access to the first I/O device the second driver portion is to send an access request to the first driver portion.

Versatile protected input/output device access and isolated servicing for virtual machines

An apparatus for secured playback is presented. In one embodiment, the apparatus includes a controller that includes a key derivation module to manage authentication and key derivation. In one embodiment, the apparatus provides a video decryption key to a graphics engine if video data portions in a data stream are retrievable without having to decrypt the data stream. In one embodiment, the apparatus also includes a decryption module to decrypt a part of data in conjunction with an encryption key to generate video information and video data. The controller then writes an encrypted version of the video data to a video buffer of a graphics engine.

Methods and apparatuses for securing playback content

In one embodiment, the present invention is directed to a bit processor that includes an execution unit to, responsive to an instruction for access of data of a first bit width, access data of a second bit width, the second bit width having a different number of bits than the first bit width when some of the data accessed includes non-stream data. Other embodiments are described and claimed.

Handling media streams in a programmable bit processor

Encoded data decoding techniques. A data decoding agent determines a data segment size for a packet that includes a header and a data segment. The data decoding agent determines a segment end location based, at least in part, on the data segment size. The data decoding agent processes subblocks of data from the data segment. The data decoding agent compares a current location to the segment end location to determine if a current subblock of data from the data segments contains the segment end location. The data decoding agent triggers an exception handler if the current subblock contains the segment end location.

Boundary detection in media streams

The architecture and techniques described herein can improve system performance with respect to the following. Communication between two interdependent hardware engines, that are part of pipeline, such that the engines are synchronized to consume resources when the engines are done with the work. Reduction of the role of software/firmware from feeding each stage of the hardware pipeline when the previous stage of the pipeline has completed. Reduction in the memory allocation for software-initialized hardware descriptors to improve performance by reducing pipeline stalls due to software interaction.

Direct memory access engine physical memory descriptors for multi-media demultiplexing operations

Techniques for maintaining an order of transactions in a multi-bus computer architecture. In an embodiment, an arbitrator receives access requests from a plurality of requestors, each access request requesting a respective access to a bus. Based on an arbitration between the access requests&#x2014;e.g. between those requestors providing the access requests&#x2014;the arbitrator may generate a grant message which triggers a carrying of a first message on the first bus. In certain embodiments, the grant message further triggers another carrying of the first message on the second bus.

Method, apparatus and system for maintaining transaction coherecy in a multiple data bus platform

The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.

Growing community of inventors

Elk Grove, CA, United States of America

Raul N Gutierrez