International Business Machines Corporation

Lockheed Martin Corporation

Raul E Acosta

Steven Alan Cordes

Robert Allen Groves

Jennifer L Lund

Joanna Rosner

Melanie L Carasso

Alfred Grill

Katherine Lynn Saenger

Marie Angelopoulos

David Edward Kotecki

Raman Gobichettipalayam Viswanathan

James H Comfort

Juan R Maldonado

Hariklia Deligianni

Christopher Vincent Jahnes

John Michael Cotte

Fuad Elias Doany

Jane M Shaw

Chandrasekhar Narayan

Edward John Yarmchuk

Panayotis Constantinou Andricacos

David Earle Seeger

Wilma Jean Horkans

Kurt R Kimmel

Michael James Cordes

Andrew T Pomerene

L Paivikki Buchwalter

Steven Allen Cordes

Judith D Olsen

Jerome Paul Silverman

Ruby Mukherjee

Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

High Q inductor with faraday shield and dielectric well buried in substrate

A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP. After planarization the fabrication of the remaining part of the solenoidal coil is fabricated as part of the metallization in the BEOL (i.e. as line/vias of the BEOL). To further increase the cross section of the solenoidal coil part of it may be built by electrodeposition through a mask on top of the BEOL layers.

Method of fabricating integrated coil inductors for IC devices

Disclosed is a capacitive electrostatic MEMS RF switch comprised of a lower electrode that acts as both a transmission line and as an actuation electrode. Also, there is an array of one or more fixed beams above the lower electrode that is connected to ground. The lower electrode transmits the RF signal when the top beam or beams are up and when the upper beams are actuated and bent down, the transmission line is shunted to ground ending the RF transmission. A high dielectric constant material is used in the capacitive portion of the switch to achieve a high capacitance per unit area thus reducing the required chip area and enhancing the insertion loss characteristics in the non-actuated state. A gap between beam and lower electrode of less than 1 &mgr;m is incorporated in order to minimize the electrostatic potential (pull-in voltage) required to actuate the switch.

MEMS RF switch with low actuation voltage

Integrated coil inductors for IC devices

Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.

Structure and fabrication method for non-planar memory elements

In the invention a pellicle mounting structural principle is provided whereby a membrane for protection of an X-ray mask is interchangeably positioned with proper spacing between the X-ray mask and the resist on the wafer in which the pattern produced by the X-ray exposure is to be formed. The mounting principle employs a combined assembly of, a membrane and spacer member subassembly together with a means for seectably separable retention to the supporting structural portion of the mask The principle accommodates membrane materials that may not be flexible and provides an ability to remove the membrane for cleaning or replacement and to removal and reassembly with ease in reestablishing the spacing with respect to the mask. The means for the selectably separable retention to the supporting structural portion of the mask involves the use of springs and elastomers, securing to the sides of the supporting structural mask ring and the bonding of the spacer member directly to the mask.

X-ray mask pellicles and their attachment in semiconductor manufacturing

A precise thickness bulk etchable wafer material, that is responsive to protection with an oxide that inhibits insertion of an etch responsiveness altering material, is assembled with a membrane material that is susceptible to deposition processes. A bulk etch then removes most of the wafer. The arrangement permits the strength and rigidity of the bulk spacer to serve to permit the finely controllable deposition processes for ultra thin and wider ranges of membrane materials, the selective protection for spacer shaping and finally, the removal by the low stress process of etching, of the unused bulk spacer material. An oxide layer is patterned on a bulk spacer material wafer that has a thickness of the gap between an X-ray mask and the to be patterned oxide. The oxide on the bulk spacer material prevents conversion, through the exposed surface of the bulk spacer material wafer, of a portion of the wafer that is to serve as the spacer to a different etch responsiveness from that of the bulk spacer material. The exposed bulk spacer material wafer is converted to a depth that will serve as the spacer and to protect the edges. The oxide is then removed. The membrane is deposited over the full surface of the bulk spacer material. The bulk wafer is removed down to the converted portion using the imparted different etch responsivness.

Structure and manufacture of X-ray mask pellicle with washer-shaped member

An inventive mirror system for use in providing reflected X-ray radiation to a mask having pattern areas and opaque areas, comprising a plurality of parallel mirror segments which are vertically positioned with respect to each other at distances approximately equal to the widths of the corresponding opaque mask areas. In operation, radiation incident on each of the mirror segments is reflected to the patterned feature areas of the mask and skips over the opaque mask areas.

Mirror for providing selective exposure in X-ray lithography

A universal mask for use in making Integrated Circuits. The individual size masks are produced on a wafer having standardized, large size membrane area. A combined X-ray blocking and membrane stiffening layer is applied on at least one side of the wafer. This stiffening/blocking layer includes an X-ray transparent region having a size commensurate with the desired exposure field and aligned therewith.

X-ray mask structure

An X-ray mask pellicle is capable of protecting the X-ray mask from contaminants and the wafer from contact with the X-ray absorber material of the mask. The X-ray mask pellicle is sufficiently thin to allow X-ray exposure at the required mask to wafer gaps yet is sufficiently durable, replaceable, tough and X-ray resistant to be used in X-ray lithography. A thin (organic or inorganic) X-ray mask pellicle to be placed covering the X-ray mask pattern area is fabricated as a thin film and attached to a support ring. A selected area of the pellicle film, tailored to cover the absorber pattern in the X-ray mask, is etched to decrease its thickness to below 2 .mu.m. If the thin film of the pellicle is not itself conductive, a thin conductive film may be coated on both sides. In an alternative embodiment, the separation between the pellicle and the X-ray mask can be achieved by forming the mask with a stepped profile.

X-ray mask pellicle

A membrane mask structure for lithography using a radiation source and steps for fabricating and using the inventive membrane mask structure. The membrane mask structure comprises the following: a support structure formed of a material which is opaque to the lithographic radiation source and comprising support members separated by window areas; a membrane layer overlaying said support members and window areas, said membrane layer comprised of material which is transparent to said radiation source; and a pattern of feature material formed on or embedded in the membrane layer, said feature material being opaque to the radiation source and said feature pattern aligning with the window areas of said support structure. The mask structure may additionally include a plurality of reference markers formed in or on said membrane layer or on said support members of said support structure. In addition, the mask structure may include a protective pellicle of radiation-transparent material, which pellicle is mounted on the surface of said support members not associated with said membrane layer in such a way as to prevent any debris from contacting the membrane areas on which the feature pattern is formed.

Membrane mask structure, fabrication and use

This invention relates to the prevention of mechanical and electrical failures in structures that are heat-treated, and more particularly relates to the use of coating layers containing Co and P on corrosible materials such as Cu. The invention has significant utility in the protection of Cu current-carrying lines in electronic structures that comprise multi layers that are subjected to heat treatments that would normally adversely affect the Cu lines. The CoP coating layer also acts to prevent interdiffusion between Cu and contact metals, such as Au.

Prevention of mechanical and electronic failures in heat-treated

A plating rate monitor includes a Wheatstone bridge, one branch of which is a monitoring resistor formed on a printed circuit board located in the same environment as an object being plated. The resistor undergoes plating at the same rate as the object. Each time the bridge becomes balanced, another resistor branch of the bridge, which is variable, is incremented by a preselected value to upset the balance. As the monitoring resistor in the plating environment undergoes plating, a change in its resistance causes the bridge to become balanced once again and the time interval for achieving this balance, for a calculated plating thickness change of the monitoring resistor, determines the plating rate.

Growing community of inventors

White Plains, NY, United States of America

Raul E Acosta