Emulex Design & Manufacturing Corporation

Emulex Corporation

Raul Bersamin Oteyza

Karl M Henson

Bradley Eugene Roach

Jim Donald Butler

David James Duckman

Vuong Cao Nguyen

Steven Gerard LeMire

Jeff Junwei Zheng

A method is disclosed for indicating a status of a transfer of data from a first device to a second device over a network. In one embodiment, the data includes one or more data frames. Each frame includes a header having one or more bits. The method includes setting a last bit of the one or more bits in the header of a last frame of the one or more data frames to a first value if the status of the transfer of data is good and setting the value of the last bit of the last data frame to a second value if the transfer of data failed. This results in a less congested, more efficient network.

Method to improve the performance of a computer network

Storing frames of data in frame buffers sized to match the frame size when the frame size is not a power-of-two number of bytes is disclosed. The buffer size is chosen to be the largest power-of-two that is less than the frame size. When a frame of data is to be stored, the buffer number of a free buffer is effectively multiplied by the buffer size to obtain a partial frame buffer address Q. The buffer size subtracted from the frame size is referred to as a residual buffer size, and the buffer number is effectively multiplied by the residual buffer size to obtain a residual frame buffer address R. The full frame buffer starting address S=Q+R. For implementations where the difference between the frame size and the buffer size is a power-of-two value, binary shifts and addition can be used instead of a multiplier.

Stacking series of non-power-of-two frame buffers in a memory array

A phase-locked loop (PLL) circuit includes multiple selectable feedback paths and a mode selector for selecting different feedback paths in different operating modes. The PLL circuit may correct for clock skew or produce a desired degree of clock skew between input and output clock signals in different operating modes.

Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modes

A frame receive queue may perform disassembly and validation operations on frames received by a node in a Fiber Channel network. The frame receive queue may store information used for later processing of the frames, e.g., header data and the first eight payload words, in an on-chip memory for fast processor access. The payload data for the frames may be stored in a larger, external memory.

Queuing fibre channel receive frames

A method whereby a fair port in a Fibre Channel Arbitrated Loop behaves unfairly during portions of its loop tenancy and behaves fairly during other portions. In a preferred implementation, the fair port establishes a first loop circuit with an initial destination port during a loop tenancy. Before relinquishing control of the loop to an arbitrating port, the fair port&mdash;under the control of a transfer protocol&mdash;establishes one or more subsequent loop circuits with other destination ports. Loop circuits are established in sequence without the fair port relinquishing control of the loop and rearbitrating. This continues until (1) the fair port establishes a loop circuit with every destination port to which it desires to exchange information; (2) a fixed time period has lapsed; and/or (3) a predefined maximum number of loop circuits are established.

Growing community of inventors

Costa Mesa, CA, United States of America

Raul Bersamin Oteyza