Stmicroelectronics (crolles 2) Sas

Stmicroelectronics (rousset) Sas

Stmicroelectronics S.r.l.

Stmicroelectronics S.a.

Stmicroelectronics (research & Development) Limited

Stmicroelectronics International N.v.

Stmicroelectronics Gmbh

Stmicroelectronics (grenoble 2) Sas

Raul Andres Bianchi

Francesco La Rosa

Antonino Conte

Bruce Rae

Simon Jeannot

Enrico Castaldo

Sebastien Lagrasta

Fausto Piazza

Benoit Froment

Laurent Favennec

Alexis Farcy

Nicolas Hotellier

Marios Barlas

Sebastien Petitdidier

Bastien Mamdy

Grégory Bidal

Isobel Nicholson

Alexandre Lopez

Mathieu Pierre Lisart

Pascal Fonteneau

Dominique Golanski

Benoît Froment

Matteo Maria Vignetti

Sébastien Petitdidier

Antonin Zimmer

Christel Marie-Noëlle Buj

Giulio Forcolin

Benoït Froment

The present disclosure relates to a process to control an optoelectronic device comprising a single-photon avalanche diode n a substrate, wherein the diode comprises a first region doped with a first type of conductivity level with a first face of the substrate and a second region doped with a second type of conductivity extending from the first face to a second face of the substrate opposed to the first face, wherein the device comprises a third conducting or semiconducting region at the second face, wherein the process comprises the application of a biasing voltage to the third region in order to generate an electric field that accelerates the charges generated in the diode.

Optoelectronic device

The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.

Pixel with an improved quantum efficiency having a micro-lens and a diffractive structure

A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.

Chip protected against back-face attacks

A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.

SPAD photodiode

Pixel with an improved quantum efficiency

An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

Integrated circuit and method of manufacturing the same

The present disclosure relates to a device that includes a photodiode having a first terminal that is coupled by a resistor to a first rail configured to receive a high supply potential and a second terminal that is coupled by a switch to a second rail configured to receive a reference potential. A read circuit is configured to provide a pulse when the photodiode enters into avalanche, and a control circuit is configured to control an opening of the switch in response to a beginning of the pulse and to control a closing of the switch in response to an end of the pulse.

Quenching of a SPAD

A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.

An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.

Integrated physically unclonable function device with a set of transistors exhibiting a random distribution of threshold voltages

A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.

Testing circuit of a longtime-constant circuit stage and corresponding testing method

A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.

Reading circuit of a long time constant circuit stage and corresponding reading method

Reading circuit with a shifting stage and corresponding reading method

An electronic circuit for providing a voltage or a current linearly dependent on temperature within a temperature range, including at least two identical MOS transistors conducting the same drain current, each transistor having a fully depleted channel which is separated from a doped semiconductor region by an insulating layer, the conductive types of the dopants of said doped semiconductor regions being different, said voltage or said current being proportional to the difference between the gate-source/drain voltages of the two transistors.

Circuit for providing a voltage or a current

Growing community of inventors

Myans, France

Raul Andres Bianchi