Lsi Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Rasoju Veerabadra Chary

Donald Albert Evans

Rahul Sahu

Rajiv Kumar Roy

Richard John Stephani

Ankur Goel

Dharmendra Kumar Rai

Jeffrey Charles Herbert

Bijan Kumar Ghosh

Dennis E Dudeck

Ronald James Wozniak

Setti Shanmukheswara Rao

Ronald Brian Steele

Christopher David Sonnek

SRAM devices are disclosed that utilize write assist circuits to improve the logical transitions of bit lines. In one embodiment, an SRAM device includes a pair of complimentary bit lines traversing a memory cell array for writing data to memory cells. The bit lines have a first end and a second end. A pair of complimentary write drivers is proximate to the first end of the bit lines that writes to the bit lines. A write assist circuit is proximate to the second end of the bit lines that receives a pre-charge signal to assist the write drivers in transitioning the bit lines from a logical zero state to a logical one state. The write assist circuit also receives a boost signal to assist the write drivers in transitioning the bit lines from a logical one state to a logical zero state.

Bit line write assist for static random access memory architectures

Single-ended read circuits for SRAM devices are disclosed for high performance sub-micron designs. One embodiment is an SRAM device that includes a memory cell array and a bit line traversing the memory cell array for reading data from memory cells of the memory cell array. A read circuit coupled to the bit line translates data stored in a memory cell from a cell voltage of the memory cells to a peripheral voltage of an output of the SRAM device while bypassing a level shifter in the read data path.

Dual rail single-ended read data paths for static random access memories

Word line assist circuits are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a pair of word lines that traverse the memory cell array for selecting memory cells. The SRAM device further includes a pair of word line drivers, each coupled to one of the word lines. The SRAM device further includes a word line assist circuit coupled to the pair of word lines that receives an enable signal. Responsive to receiving the enable signal, the word line assist circuit assists the first word line driver and the second word line driver in transitioning their respective word lines from a logic level zero to a logic level one in response to a voltage differential between the word lines.

Differential latch word line assist for SRAM

A decoder circuit to decode an address for accessing a memory cell in a memory array includes address latch circuitry, inverter circuitry, and first address pre-decode circuitry. The address latch circuitry receives an address signal and generates address holding signals during a setup period. The address latch circuitry latches the address holding signals during an address hold period following the setup period. The inverter circuitry receives the address signal and generates a complementary address signal. The first address pre-decode circuitry decodes the address signal and the address holding signals during the setup period to generate a first pre-decode address signal at an output of the first address pre-decode circuitry. In addition, the first address pre-decode circuitry decodes the address holding signals during the address hold period to maintain the first pre-decode address signal at the output of the first address pre-decode circuitry.

Address decoding circuits for reducing address and memory enable setup time

A memory tracking circuit activates a reset signal that resets a word-line pulse generator to switch the memory from an access state to a recess state. Activation is based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. If the memory is in a fast PVT condition such that the gate delay is of less duration than, or substantially equal to, the propagation delay, then a slow-down circuit delays activation of the reset signal to allow sufficient access margin. The delay in the latter case is less than that in the former case. If the memory is in a slow PVT condition such that the gate delay is longer than the propagation delay, then the slow-down circuit does not delay activation of the reset signal to prevent excess access margin.

Adjusting access times to memory cells based on characterized word-line delay and gate delay

A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. The tracking circuit (i) extends the discharge duration when one or more of (a) the propagation delay and (b) the transistor-based gate delay is shorter than an uncontrolled discharge duration of the tracking bit-line, and (ii) does not extend the discharge duration otherwise. Based on the discharge duration, the tracking circuit activates a reset signal that resets a clock-pulse generator to switch the memory from an access operation to a recess state. Controlling the discharge duration, and consequently the reset signal, based on the propagation delay and the gate delay allows the clock-pulse generator to adjust access times to account for the memory array configuration and process, temperature, and voltage conditions.

Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delay

A dual rail memory operable at a first voltage and a second voltage includes an input circuit, an output circuit and a clock generator circuit coupled with the input circuit. The input circuit is operable to receive at least a first input signal referenced to the first voltage and to generate a second input signal referenced to the second voltage. The output circuit is operable to receive at least a first output signal referenced to the second voltage and to generate a second output signal referenced to the first voltage. The clock generator circuit is operable to receive a first clock signal referenced to the first voltage and to generate a second clock signal referenced to the second voltage, a logic state of the second clock signal being a function of a logic state of the first clock signal.

Dual rail power supply scheme for memories

A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.

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Bengaluru, India

Rasoju Veerabadra Chary