Sandisk Technologies Inc.

Rasmus Madsen

Martin Lueker-Boden

Lunkai Zhang

Mark Myran

Christoffer Holm Kjølbæk

When a memory system supports different read modes with different read latencies, such as reference read and self-referenced read, read data conflicts can occur for data returned from the memory cells in response to the issued read commands. To support such mixed read modes, embodiments for the memory controller can include separate queues for fast read commands and slow read commands and coordinate the issuing of the two command types. A mixed read coordinator can track issued slow read commands and determine whether a fast read command can be issued. The issued commands are ordered such that they are correctly associated with the read data returned from the memory cells.

Supporting mixed read in non-volatile memory controller

A decryption engine can decrypt encrypted data read from a physical address in a memory of a data storage device. To decrypt the data, the decryption engine can use a tweak value that is generated from a logical address associated with the physical address. To reduce latency, the tweak value can be generated in parallel with the translation of the logical address to the physical address. The tweak value can be stored in a tweak buffer in the decryption engine until needed and can be indexed by a tag associated with a process in a host that is requesting the data. The tweak buffer can use static random-access memory (SRAM) or a content-addressable memory (CAM), for example. Other embodiments are provided.

Data storage device and method for hiding tweak generation latency

Technology is disclosed for controlling reads in a memory device supporting different types of reads having different performance times (e.g., a relatively fast read such as a globally-referenced read and a slower read such as a self-referenced read). The data out latencies of the different read types may be different to accommodate the different performance times. The memory controller may mix the different types of reads. The memory controller tracks expected usage of the data bus and schedules read commands accordingly to avoid data collisions. A countdown timer may be used to track the earliest clock cycle at which the memory device may return data for a new read command to be issued. The memory controller may record what clock cycles the data bus is projected to be occupied with data and schedule read commands based on the projected data bus occupancy to avoid data collisions.

Memory controller support for mixed read

A control circuit for a non-volatile memory array includes an interface to receive requests, a common request queue connected to the interface and a common request buffer connected to the common request queue. The common request buffer is configured to receive the requests from the common request queue in their received order and buffer unfinished requests directed to memory addresses such that for any address in the non-volatile memory array no more than one unfinished request is in the common request buffer.

Growing community of inventors

Copenhagen, Denmark

Rasmus Madsen