International Business Machines Corporation

Globalfoundries Inc.

Advanced Micro Devices Corporation

Adeia Semiconductor Bonding Technologies Inc.

Rasit Onur Topaloglu

Sami Rosenblatt

Markus Brink

Stephen Edward Greco

Jared Barney Hertzberg

Kafai Lai

Werner A Rausch

Martin O Sandberg

Vincent James McGahay

Naftali Eliahu Lustig

Dongbing Shao

Vivekananda P Adiga

Matthew S Angyal

Zheng Xu

Chandrasekharan Kothandaraman

Vivian Zhang Di Tore

Fang Lu

Dureseti Chidambarrao

Lars W Liebmann

Nadiya Kochura

Jonathan Zanhong Sun

Judy Xilin An

Jung-Suk Goo

Geng Han

Peter A Smith

Matthias Georg Gottwald

Leon Stok

Ian P Stobert

Hongmei Li

Yuping Cui

Christine Mary Bunke

Baaba Kyerewaa Forster-Forson

Joan Mccarthy-Griffin

Aline Wilkins

Jeremy R Tolbert

An apparatus for a fastening verification structure includes a fastener disposed in a cavity, where a leading end of the fastener is configured to press a non-insulated contact pad. The first end of a first lead electrically coupled to the fastener and a second end of the first lead electrically coupled to a power source. The first end of a second lead electrically coupled to the non-insulated contact pad and a second end of the second lead electrically coupled to a visual indicator. The first end of a third lead electrically coupled to the visual indicator and a second end of the third lead electrically coupled to the power source.

Structure for fastening verification

A method, computer system, and a computer program product for order compliance is provided. The present invention may include determining a shipping destination for an order request received from a user, wherein the order request includes one or more items. The present invention may include generating a digital twin for each of the one or more items in the order request. The present invention may include determining a compliance of the order request with a plurality of importation requirements of the shipping destination based on an analysis of the digital twin for each of the one or more items. The present invention may include generating a compliance report for the order request, wherein the compliance report includes at least a compliance status of each item included in the order request.

Methods, systems, and computer program products for order compliance tracking of electronic components

Devices, systems, and/or methods that can facilitate local heating of a superconducting flux biasing loop are provided. According to an embodiment, a device can comprise a substrate having a superconducting flux bias circuit comprising a biasing loop coupled to a flux controlled qubit device. The device can further comprise a heating device coupled to the biasing loop.

Flux bias line local heating device

Devices, systems, and/or methods that can facilitate local heating of a superconducting flux biasing loop are provided. According to an embodiment, a method can comprise forming on a substrate a biasing loop and a flux controlled qubit device of a superconducting flux bias circuit. The method can further comprise forming a heating device on the substrate to couple the heating device to the biasing loop.

Fabrication of a flux bias line local heating device

A semiconductor structure includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.

Two dimension material fin sidewall

Aspects of the invention include setting a fill mode for a border region of a layer of a macro of an integrated circuit. The border region has a depth defined by a multiple of the size of a tile used to select an area of the integrated circuit for implementation of a design rule check, and the fill mode indicates a fill percentage value or level of fill to be implemented in the border region of the layer of the macro. A fill of the border region of the layer of the macro is performed based on the fill mode. The integrated circuit is finalized and fabricated based on the performing of the fill and passing the design rule check.

Integrated circuit development using density-aware border fill

Systems and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter, transmitter, and/or antenna can be positioned above a superconducting qubit chip having a Josephson junction coupled to a set of one or more capacitor pads. The radio frequency emitter, transmitter, and/or antenna can emit an electromagnetic signal onto the set of one or more capacitor pads. The capacitor pads can function as receiving antennas and therefore receive the electromagnetic signal. Upon receipt of the electromagnetic signal, an alternating current and/or voltage can be induced in the capacitor pads, which current and/or voltage thereby heat the pads and the Josephson junction. The heating of the Josephson junction can change its physical properties, thereby annealing the Josephson junction. In another example, the emitter can direct the electromagnetic signal to avoid unwanted annealing of neighboring qubits on the superconducting qubit chip.

Antenna-based qubit annealing method

Systems, computer-implemented methods, and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a first antenna can be positioned above a superconducting qubit chip having a first Josephson junction and a second Josephson junction. The first antenna can direct a first electromagnetic wave toward the first Josephson junction. A first length of a first defined vertical gap, between the first antenna and the superconducting qubit chip, can be sized to cause the first electromagnetic wave to circumscribe a first set of one or more capacitor pads of the first Josephson junction, thereby annealing the first Josephson junction, without annealing the second Josephson junction. In another example, the first length of the first defined vertical gap can be a function of a model of the first electromagnetic wave as a cone, wherein the cone originates from the first antenna and extends toward the superconducting qubit chip.

Methods for annealing qubits with an antenna chip

A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.

Self-aligned double patterning with spacer-merge region

Techniques related to vertical silicon-on-metal superconducting quantum interference devices and method of fabricating the same are provided. Also provided are associated flux control and biasing circuitry. A superconductor structure can comprise a silicon-on-metal substrate that can comprise a first superconducting layer, comprising a first superconducting material, between a first crystalline silicon layer and a second crystalline silicon layer. The superconducting structure can also comprise a first via comprising a first Josephson junction and a second via comprising a second Josephson junction. The first via and the second via can be formed between the first superconducting layer and a second superconducting layer, comprising a second superconducting material. An electrical loop around a defined area of the second crystalline silicon layer can comprise the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer.

Vertical silicon-on-metal superconducting quantum interference device

Systems, computer-implemented methods, and computer program products that can facilitate quantum circuit topology selection based on frequency collisions between qubits, are described. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a simulation component that simulates operation of qubits in a subgraph topology of a graph representing a topology of a quantum circuit to determine a quantity of frequency collisions between the qubits. The computer executable components can further comprise a selection component that selects a quantum circuit topology based on the quantity of frequency collisions between the qubits.

Quantum circuit topology selection based on frequency collisions between qubits

A method, apparatus and computer program product for using a volumetric CAPTCHA display to verify that a human is present at a computer. Responsive to a request for a computer resource, a volumetric CAPTCHA is displayed in a user interface at the computer. The volumetric CAPTCHA has a first three dimensional (3D) feature and a second 3D feature. The user is prompted to answer a question about the first 3D feature of the volumetric CAPTCHA display. The received user response to the question is evaluated for correctness in describing the first 3D feature of the volumetric CAPTCHA. In response to the received user response being correct, the user is allowed access to the computer resource. The first 3D feature and the second 3D feature have a relationship with each other in the volumetric CAPTCHA.

Volumetric display-based CAPTCHA system

Aspects of the invention provide means for addressing layout retargeting shortfalls. Initially, an original design shape in the layout is allowed to be simulated by process simulation to form process simulation contours. A polygon is then fitted to the process simulation contours to form a fitted simulated shape. Subsequently, whether the fitted simulated shape differs from the original design shape is detected. The process simulation may reflect the changes to the layout that occur at a foundry as part of a retargeting process. Advantageously, addressing a layout for retargeting shortfalls in accordance with aspects of the invention is likely to result in manufactured semiconductor devices having higher yields and reliability than those produced from a like layout that is not addressed in this manner.

Addressing layout retargeting shortfalls

A true random number generator (TRNG) device having a magnetic tunnel junction (MTJ) structure coupled to a domain wall wire. The MTJ structure is formed of a free layer (FL) and a reference layer (RL) that sandwiches a tunnel barrier layer. The free layer has anisotropy energy sufficiently low to provide stochastic fluctuation in the orientation of the magnetic state of the free layer via thermal energy. The domain wall wire is coupled to the MTJ structure. The domain wall wire has a domain wall. Movement of the domain wall tunes a probability distribution of the fluctuation in the orientation of the magnetic state of the free layer. The domain wall can be moved by application of a suitable current through the wire to tune the probability distribution of 1's and 0's generated by a readout circuit of the TRNG device.

Magnetic tunnel junction based true random number generator

Systems and techniques providing suitable chip structures for facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter can comprise a voltage-controlled oscillator and an antenna. The voltage-controlled oscillator can receive power-on signals from a microcontroller, thereby causing the voltage-controlled oscillator to generate an electromagnetic wave. The antenna can then direct the electromagnetic wave onto a set of one or more capacitor pads of a Josephson junction on a superconducting qubit chip, thereby annealing the Josephson junction. In another example, a voltage regulator and a digital-to-analog converter or digital-to-digital converter can be coupled in series between the microcontroller and the voltage-controlled oscillator, thereby allowing the voltage-controlled oscillator to be voltage and/or frequency tunable and eliminating the need for external power routing as compared to photonic laser annealing. In yet another example, a bipolar-junction and complementary metal-oxide semiconductor stack construction can be employed.

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Poughkeepsie, NY, United States of America

Rasit Onur Topaloglu