Intel Corporation

Rasika Subramanian

Francesc Guim Bernat

Mark A Schmisseur

Lidia Warnes

Durgesh Srivastava

Kshitij Arun Doshi

Tsung-Yuan Charles Tai

Ren Wang

Ravishankar Iyer

Andrew J Herdrich

David Zimmerman

Yipeng Wang

Steen K Larsen

Bin Li

Zhu Zhou

An apparatus and method for closed loop dynamic resource allocation. For example, one embodiment of a method comprises: collecting data related to usage of a plurality of resources by a plurality of workloads over one or more time periods, the workloads including priority workloads associated with one or more guaranteed performance levels and best effort workloads not associated with guaranteed performance levels; analyzing the data to identify resource reallocations from one or more of the priority workloads to one or more of the best effort workloads in one or more subsequent time periods while still maintaining the guaranteed performance levels; reallocating the resources from the priority workloads to the best effort workloads for the subsequent time periods; monitoring execution of the priority workloads with respect to the guaranteed performance level during the subsequent time periods; and preemptively reallocating resources from the best effort workloads to the priority workloads during the subsequent time periods to ensure compliance with the guaranteed performance level and responsive to detecting that the guaranteed performance level is in danger of being breached.

Apparatus and method for a closed-loop dynamic resource allocation control framework

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to allocate a first memory portion to a first application as a combination of a local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, and manage a first memory balloon associated with the first memory portion based on two or more memory tiers associated with the local memory and the remote memory. Other embodiments are disclosed and claimed.

Ballooning for multi-tiered pooled memory

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to provide an interface to a pooled memory that is configured as a combination of local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, allocate respective memory portions of the pooled memory to respective tenants, associate respective memory balloons with the respective tenants that correspond to the allocated respective memory portions, and manage the respective memory balloons based on the respective tenants and two or more memory tiers associated with the pooled memory. Other embodiments are disclosed and claimed.

Tenant based allocation for pooled memory

Examples described herein can be used to determine and suggest a computing resource allocation for a workload request made from an edge gateway. The computing resource allocation can be suggested using computing resources provided by an edge server cluster. Telemetry data and performance indicators of the workload request can be tracked and used to determine the computing resource allocation. Artificial intelligence (AI) and machine learning (ML) techniques can be used in connection with a neural network to accelerate determinations of suggested computing resource allocations based on hundreds to thousands (or more) of telemetry data in order to suggest a computing resource allocation. Suggestions made can be accepted or rejected by a resource allocation manager for the edge gateway and the edge server cluster.

Accelerated resource allocation techniques

A computing device, a method and a system to control power. The computing device is configured to be used as part of a network fabric including a plurality of nodes and a plurality of pooled accelerators coupled to the nodes. The computing device includes: a memory storing instructions; and processing circuitry configured to perform the instructions. The processing circuitry is to receive respective requests from respective ones of the plurality of nodes, the requests addressed to a plurality of corresponding accelerators, each of the respective requests including information on a kernel to be executed by a corresponding accelerator, on the corresponding accelerator, and on a performance target for execution of the kernel. The processing circuitry is further to, based on the information in said each of the respective requests, control a power supply to the corresponding accelerator.

Multi-criteria power management scheme for pooled accelerator architectures

Growing community of inventors

Hillsboro, OR, United States of America

Rasika Subramanian