International Business Machines Corporation

Advanced Micro Devices Corporation

Globalfoundries Inc.

University of Toledo

Rashmi Jha

Michael Patrick Chudzik

Naim Moumen

Vijay Narayanan

Keith Kwong Hon Wong

Renee Tong Mo

Vamsi Krishna Paruchuri

Richard Stephan Wise

Ravikumar Ramachandran

Siddarth A Krishnan

Dae-Gyu Park

Martin Michael Frank

Yue Liang

Herbert Lei Ho

Wesley Charles Natzle

Kathryn Turner Schonenberg

Xi Li

Mark J Hurley

Ying H Tsang

Wiliam K Henson

Takashi Ando

Sivananda K Kanakasabapathy

Ying Di Zhang

Eduard Albert Cartier

Unoh Kwon

Richard Anthony Conti

William K Henson

Troy Lawrence Graves-Abe

Ricardo Alves Donaton

Michael Abramovich Gribelyuk

Michelle Leigh Steen

Rick J Carter

Mark Todhunter Robson

Branden Long

Jorhan Ordosgoitti

Michael P Chudzik

Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.

Changing effective work function using ion implantation during dual work function metal gate integration

A nanoelectric memristor device includes a first electrode and a layer of oxygen-vacancy-rich metal oxide deposited upon a surface of the first electrode. A layer of oxygen-rich/stochiometric metal oxide is deposited upon a surface of the oxygen-vacancy-rich metal oxide layer that is opposite from said first electrode. At least one of the oxygen-vacancy-rich metal oxide and oxygen-rich/stochiometric metal oxide layers is doped with one of a magnetic and a paramagnetic material. A second electrode is adjacent to a surface of the oxygen-rich/stochiometric metal oxide layer that is opposite from the oxygen-rich/stochiometric metal oxide layer.

Nanoelectric memristor device with dilute magnetic semiconductors

The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.

Dual metal and dual dielectric integration for metal high-K FETs

CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a 'p' interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the 'p' interface control layer is aluminum oxide. The NFET device may have an &#x201c;n&#x201d; interface control layer. The materials of the &#x201c;p&#x201d; and &#x201c;n&#x201d; interface control layers are differing materials. The &#x201c;p&#x201d; and &#x201c;n&#x201d; interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned &#x201c;p&#x201d; and &#x201c;n&#x201d; interface control layers are also disclosed.

Gate effective-workfunction modification for CMOS

Structure and method of improving the performance of metal gate devices by depositing an in-situ silicon (Si) cap are disclosed. A wafer including a substrate and a dielectric layer is heated through a degas process, and then cooled to approximately room temperature. A metal layer is then deposited, and then an in-situ Si cap is deposited thereon. The Si cap is deposited without vacuum break, i.e., in the same mainframe or in the same chamber, as the heating, cooling and metal deposition processes. As such, the amount of oxygen available for interlayer oxide regrowth during subsequent processing is reduced as well as the amount oxygen trapped in the metal gate.

In-situ silicon cap for metal gate electrode

Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N/H) or ammonia (NH) may be used to remove the photoresist mask. With the use of the plasma nitrogen-hydrogen forming gas (N/H) or a plasma ammonia (NH), no apparent organic residual is observed.

Method for forming dual high-K metal gate using photoresist mask and structures thereof

A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In one embodiment, the PFET includes an n-type doped silicon well (N-well), a gate stack including: a doped band engineered PFET threshold voltage (Vt) work function tuning layer over the N-well; a tailored dielectric layer over the doped band engineered PFET Vt work function tuning layer, the tailored dielectric layer constituted by a high dielectric constant layer over the doped band engineered PFET Vt work function tuning layer and an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer; and a metal over the NFET Vt work function tuning layer.

PFET with tailored dielectric and related methods and integrated circuit

In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.

Structure and method to control oxidation in high-k gate structures

Dual metal and dual dielectric integration for metal high-k FETs

The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

Dielectric spacer removal

Method for forming dual high-k metal gate using photoresist mask and structures thereof

A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiOand alpha-silicon layers or a dBARC layer.

Semiconductor device having dual metal gates and method of manufacture

A metal gate and high-k dielectric device includes a substrate, an interfacial layer on top of the substrate, a high-k dielectric layer on top of the interfacial layer, a metal film on top of the high-k dielectric layer, a cap layer on top of the metal film and a metal gate layer on top of the cap layer. The thickness of the metal film and the thickness of the cap layer are tuned such that a target concentration of a cap layer material is present at an interface of the metal film and the high-k dielectric layer.

Method for tuning the threshold voltage of a metal gate and high-k device

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Toledo, OH, United States of America

Rashmi Jha