Cadence Design Systems, Inc.

Raquel Lara Dos Santos Pereira

Abner Luis Panho Marciano

Fabiano Cruz Peixoto

Matheus Nogueira Fonseca

Mirlaine Aparecida Crepalde

Thamara Karen Cunha Andrade

Adriana Cassia Rossi De Almeida Braz

Rodrigo Fonseca Rocha Soares

Laiz Lipiainen Santos

Guilherme Seminotti Braga

Lucas Duarte Prates

Rafael Gontijo Hamdan

Caio Texeira Campos

Rodrigo Da Silva Mantini Viana

Rodolfo Santos Teixeira

Hudson Dyele Oliveira

Bruno Andrade Pereira

Breno Rodrigues Guimares

Luis Humberto Rezende Barbosa

Caio Alves Furtado

Breno Augusto Dias Vitorino

In the described examples, a model impact monitor can include an electronic design automation (EDA) manager that communicates with a plurality of EDA programs, wherein each EDA program generates a model set for a register-transfer level (RTL) design comprising a list of RTL operations. The model impact monitor can also include an adaptive model interface that records changes to the RTL operations of the RTL design and measures a change in performance characteristics of each of the plurality of EDA programs based on a respective one of the changes in the RTL operations of the RTL design.

Adaptive model interface for a plurality of EDA programs

The present disclosure relates to a method for use in the formal verification of an electronic circuit. Embodiments may include receiving, using a processor, a portion of an electronic circuit design and analyzing a syntactic structure of a string associated with the electronic circuit design. Embodiments may also include generating a parse tree, based upon, at least in part, the analysis and traversing the parse tree to identify one or more conditional nodes. Embodiments may further include generating a new node for each of the one or more conditional nodes and displaying, at a graphical user interface, a check, at least one of the one or more conditional nodes or the new node prior to performing either register-transfer-level RTL synthesis or final synthesis.

System, method, and computer program product for over-constraint/deadcode detection in a formal verification

Disclosed are techniques for implementing formal verification of an electronic design. These techniques identify a target property for verification in a hierarchical electronic design that has a plurality of hierarchies and perform hierarchical synthesis on a hierarchy or a portion thereof in the plurality of hierarchies while black-boxing a remaining portion of the hierarchical electronic design. Cone of influence (COI) data that is relevant to the target property may be determined at least by extracting the cone of influence data from a hierarchically synthesized hierarchy or portion of the hierarchy or the portion thereof. At least the cone of influence data may be forwarded to a formal engine that uses the cone of influence data to verify the target property.

Methods, systems, and computer program product for verifying an electronic design

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Belo Horizonte, Brazil

Raquel Lara Dos Santos Pereira