Agile Power Switch 3D-Integration Apsi3d

Irt Saint Exupery (Aese)

Ecole Nationale D'ingenieurs De Tarbes

Raphaël Riva

Jean-Michel Francis Reynes

Jacques Pierre Henri Favre

Paul-Etienne Joseph Vidal

Bernard José Charles Du Trieu De Terdonck

Baptiste Louis Jean Trajin

Some embodiments are directed to a method of determining a sintering thermal impedance of a sintering layer by: providing a substrate having a predetermined substrate thermal impedance and disposing the sintering layer on the substrate forming with the sintering layer a stack. Placing at least one semiconductor die, that includes a semiconductor element with at least two element electrodes on the sintering layer. Injecting an electrical current through the at least two element electrodes for measuring a temperature sensitive parameter of the semiconductor element. Heating the stack with a predetermined heat power and determining, while sintering, a semiconductor element temperature from the measured temperature sensitive parameter. Measuring a stack temperature and determining a stack thermal impedance by subtracting the semiconductor element temperature from the stack temperature and dividing by the predetermined heat power, and subtracting the predetermined substrate thermal impedance from the stack thermal impedance.

Method of determining thermal impedance of a sintering layer and a measurement system

Some embodiments relate to a semiconductor power device that includes a first substrate, a second substrate, a stack and an interconnect structure. The first substrate includes a first patterned electrically conductive layer on a first surface and a switching semiconductor element. The second substrate includes a second surface facing the first surface and a second patterned electrically conductive layer on the second surface. The stack includes an electrically conductive track and a layer of a dielectric material. The layer of the dielectric material is provided on the first or second patterned electrically conductive layer and the layer of the dielectric material isolates the electrically conductive track from the patterned electrically conductive layer on which the stack is provided. The interconnect structure provides at least one electrical connection electrically conductive layers or areas of the substrates.

Semiconductor power device comprising additional tracks and method of manufacturing the semiconductor power device

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Ger, France

Raphaël Riva