International Business Machines Corporation

Raphael Peter Robertazzi

Peilin Song

Franco Stellari

Keith Aelwyn Jenkins

Barry P Linder

Emmanuel Yashchin

Alan Weger

James H Stathis

Emily A Ray

Kevin Geoffrey Stawiasz

Eren Kursun

Alberto Valdes Garcia

John Francis Bulzacchelli

Chen-Yong Cher

Gary William Maier

Matthew Beck

A system comprises a superconducting quantizing inductor and superconducting control circuitry, which is coupled to the superconducting quantizing inductor to form a superconducting loop, and which is configured to selectively inject a quantized amount of positive or negative current into the superconducting loop to generate a quantized circulating current in the superconducting loop. The quantized circulating current comprises a time-varying or static circulating current. The superconducting control circuitry comprises first and second current generator circuits which comprise a first and second plurality of Josephson junctions, respectively, which are configured to inject quantized amounts of positive current and negative current into the superconducting loop in response to single flux quantum pulses. The first and second current generator circuits comprise respective first and second current distribution networks that are configured to distribute circulating current in the superconducting loop to the respective Josephson junctions without causing switching of the Josephson junctions.

Single flux quantum circuitry for quantized flux bias control

A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.

Method for the characterization and monitoring of integrated circuits

Methods and systems of detecting chip degradation are described. A processor may execute a test on a device at a first time, where the test includes executable instructions for the device to execute a task under specific conditions relating to a performance attribute. The processor may receive performance data indicating a set of outcomes from the task executed by the device during the test. The processor may determine a first value of a parameter of the performance attribute based on the identified subset. The processor may compare the first value with a second value of the parameter of the performance attribute. The second value is based on an execution of the test on the device at a second time. The processor may determine a degradation status of the device based on the comparison of the first value with the second value.

Detection of performance degradation in integrated circuits

A method for characterizing an integrated circuit that selecting at least two devices from an integrated circuit for measuring light emission, wherein each of the at least two devices have experienced a different level of stress, applying power to the integrated circuit, and measuring the light emission from the at least two devices. The method also includes comparing the light emission that is measured from the at least two devices, wherein a difference between the light emission that is measured from the at least two devices greater than a predetermined ratio indicates that at least one of the devices from the at least two devices has a below specification performance.

A method and system are provided for chip testing. The method includes selectively deploying a chip for future use or discarding the chip to prevent the future use, responsive to a stress history of the chip determined using a non-destructive test procedure. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto. The test procedure further includes ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks. The test procedure also includes calculating a sum by summing the plurality of pattern ranks. The sum calculated during an initial performance of the test procedure is designated as a baseline, and the sum calculated during a subsequent performance of the test procedure is compared to a threshold derived from the baseline to determine the stress history of the chip.

Non-destructive analysis to determine use history of processor

A software signature transceiver includes a signature receiver configured to couple to a programmable electronic device and sense a signature signal generated by the programmable electronic device, wherein the signature signal varies according to computer program codes executed by the programmable electronic device, and a signature transmitter operably connected to the signature receiver, the signature transmitter configured to transmit a signature transmission signal corresponding to the signature signal. A corresponding method to use the software signature transceiver and a software monitoring device to determine whether unknown software is executing on a programmable electronic device is also disclosed herein. A corresponding system comprising the programmable electronic device, the software signature transceiver, and a software monitoring device is also disclosed herein.

Remote monitoring of software

A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip. The method further includes repeating the test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each pattern based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the pattern ranks. The sum calculated by the ascertaining step is designated as the baseline, and the sum calculated by the repeating step is compared to the threshold to determine the stress history of the chip under test.

A design-for-test (DFT) architecture for testing a three dimensional (3D) integrated circuit, may comprise a two dimensional (2D) silicon layer n&#x2212;1 and a 2D silicon layer n connected together with a through silicon via (TSV) having a first side and a second side; scannable latch circuits on said first side and said second side of said TSV, wherein said scannable latch circuits: control flow of data between said layer n&#x2212;1 and said layer n and allow said TSV to be verified; allow launch and capture clocks to be applied with variable delay in order to perform an alternating current delay fault test between said layer n&#x2212;1 and said layer n; and have a quiescent state supply current (IDDq) test function built in which allows selection of an input load for a unidirectional signal connection between said layer n&#x2212;1 and said layer n.

Method for testing through silicon vias in 3D integrated circuits

Testing of a three-dimensional (3D) integrated circuit includes defining a first group of parts by a region and/or layer on the 3D integrated circuit. The testing further includes applying a first intensity of stress test conditions to the first group of parts. The testing also includes defining a second group of parts by a region and/or layer on the 3D integrated circuit that is different from the first group of parts. The testing further includes and applying a second intensity of stress test conditions to the second group of parts. The second intensity of stress test conditions is greater than the first intensity and is determined by sensitivities identified for each of the first and second group of parts. A determination is made whether the 3D integrated circuit passed the testing based upon results of application of the first and second intensities of stress test conditions.

Three-dimensional (3D) stacked integrated circuit testing

Noise reduction for application of structural test patterns to a Device Under Test (DUT) is accomplished with a capacitor 'booster' bypass network on the probe card in which the capacitors are charged to a much higher voltage Vthan the DUT power supply voltage VDD. Charging the capacitors to a voltage N&#xd7;VDD allows the buster network to store N times the charge of a conventionally configured capacitance network, and effectively provides N times the capacitance of the original network in the same physical space.

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Ossining, NY, United States of America

Raphael Peter Robertazzi