International Business Machines Corporation

Raphael C Polig

Heiner Giefers

Christoph M Angerer

Christoph Hermann Hagleitner

Alessandro Curioni

Tobias Werner

Mitra Purandare

Konstantinos Bekas

Kubilay Atasu

Silvio Dragone

Michael B Kugel

Akihiro Nakayama

Tong Xu

Jan Van Lunteren

Silke Penth

Alexander Albert Woerner

Matteo Manica

Peter W J Staar

Costas Bekas

Yuen H Chan

Stefan Payer

Frederick Ralph Reiss

Maria Rodriguez Martinez

Dionysios Diamantopoulos

Yves G Ineichen

Roland Mathis

Rajdeep Mukherjee

Anthony Parent

A field programmable gate array (FPGA) may be used for inference of a trained deep neural network (DNN). The trained DNN may comprise a set of parameters and the FPGA may have a first precision configuration defining first number representations of the set of parameters. The FPGA may determine different precision configurations of the trained DNN. A precision configuration of the precision configurations may define second number representations of a subset of the set of parameters. For each precision configuration of the determined precision configurations a bitstream file may be provided. The bitstream files may be stored so that the FPGA may be programmed using one of the stored bitstream files for inference of the trained DNN.

Deep neural network on field-programmable gate array

A random sequence generation of defined values may be provided. A method comprises pre-loading a RAM block with an initial list comprising the defined values of a sequence of values to be updated, and shuffling the defined values of the sequence using a counter and a random offset for indices in the list.

Random sequence generation for gene simulations

Analysis of genetic disease progression may be provided. Data about a set of molecular status may be received. A dynamic prediction model of molecular interactions may be provided over time. The molecular statuses of the set over time may be determined using the dynamic prediction model. The determined molecular statuses may be clustered by applying an interaction-aware metric for the analysis of the genetic disease progression.

Interactive-aware clustering of stable states

The invention is notably directed to a computing system configured to perform linear algebraic operations. The computing system comprises a co-processing module comprising a co-processing unit. The co-processing unit comprises a parallel array of bit-serial processing units. The bit-serial processing units are adapted to perform the linear algebraic operations with variable precision. The invention further concerns a related computer implemented method and a related computer program product.

Bit-serial linear algebra processor

An example of an embodiment is directed to a computer-implemented method for providing a cloud service to execute a computing task of a model specification. The method includes receiving, by the cloud service, the model specification and input data for the model specification from a user. The method further includes generating, by the cloud service, native code from the model specification and executing, by the cloud service, the computing task by executing the native code as a native process with the input data. The method also includes providing, by the cloud service, results of the computing task to the user. Other embodiments further concern a related computing system and a related computer program product.

Native code generation for cloud services

Generating an abstract model of the behavior of a hardware and/or software design. A learning framework learns an unknown regular language that represents the behaviors of the hardware and/or software logic which do not violate a specified property that the abstract model is required to satisfy. The framework receives input data including the specified property, concrete models of the behavior of the hardware and/or software; and an alphabet of all symbols that are allowed to occur in any string that can be defined in the unknown regular language, each symbol representing an event in the hardware and/or software. The framework generates an abstract model of the behavior of the hardware or software design by checking whether a sequence of events in a concrete model satisfies the specified property and outputs the generated abstract model.

Learning framework for software-hardware model generation and verification

A cascaded finite-state-transducer array includes a plurality of finite-state-transducers, the finite-state-transducers being distributed in space. The finite-state-transducer array is configured with dedicated data transfer channels between the finite-state-transducers to transfer specific data types. Each data stream on a dedicated data transfer channel may transmit a particular data type, which may be sorted in increasing order of start offsets or token IDs.

Hardware compilation of cascaded grammars

A computing system comprising a central processing unit (CPU), a memory processor and a memory device comprising a data array and an index array. The computing system is configured to store data lines comprising data elements in the data array and to store index lines comprising a plurality of memory indices in the index array. The memory indices indicate memory positions of data elements in the data array with respect to a start address of the data array. There is further provided a related computer implemented method and a related computer program product.

Index based memory access using single instruction multiple data unit

According to some embodiments, a computer-implemented method for performing sparse matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) module comprising a k-stage pipeline is described. The method may include interleaving k-stage threads on the k-stage pipeline comprising a plurality of threads tto t, wherein a first result of thread tis ready one cycle after the first input of thread tis fed into the pipeline, and outputting a result matrix Y.

Sparse matrix multiplication using a single field programmable gate array module

Differential data access. A method for storing and reading data elements to and from a memory is provided. The method includes storing a data element as a base word in a first precision, storing at least one delta word including additional information related to a second precision version of the stored data element, and reading the base word and the at least one delta word of the stored data element to access the data element in the second precision.

Precision data access using differential data

Embodiments of the present invention provide methods, computer program products, and systems for solving a linear equation system using a hardware-implemented extended solver, wherein a calculation precision is adapted in each iteration step of a solving process is provided. Embodiments of the present invention can be used to perform on-the-fly interpolations using the data associated with the highest resolution of the three-dimensional finite element voxel model to a lower resolution than the highest resolution as well as to perform solving computations of the solving process in the lower resolution.

Linear FE system solver with dynamic multi-grip precision

A non-deterministic finite state machine module for use in a regular expression matching system. The system includes a computational unit implementing a non-deterministic finite state machine representing a regular expression, wherein the computational unit is configured to: receive an input data stream, wherein an occurrence of the regular expression is determined, and an activation signal; process the input data stream with respect to the non-deterministic finite state machine depending on the activation signal; and provide at least one branch data output for initializing an additional non-deterministic finite state machine module if the processing of an element of the input data stream according to the non-deterministic finite state machine results in a branching of a processing thread.

Non-deterministic finite state machine module for use in a regular expression matching system

A system and method to hardware-accelerate finite state transducer libraries and their compilation toolchains. In an embodiment, a computer-implemented method for partitioning an UIMA-PEAR file into software-based and hardware-accelerated components may comprise creating a data-flow graph representation of the UIMA-PEAR-file, flattening hierarchies of the data-flow graph representation, and selecting the components to be hardware accelerated from the flattened hierarchies of the data-flow graph representation based on data dependencies of data types produced and consumed by each component of the flattened data-flow graph.

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Dietkon, Switzerland

Raphael C Polig