Xilinx, Inc.

Raoul Badaoui

Xiaojian Yang

Sridhar Krishnamurthy

Grigor S Gasparyan

Mehrdad Eslami Dehkordi

Marvin Tom

Maogang Wang

The disclosed approaches involve evaluating by a design tool executing on a computer system, a plurality of nets of a circuit design for individual levels of suitability for cutting each net into a cut net that crosses a partition boundary between a plurality of partitions of an integrated circuit (IC) device. The design tool partitions the circuit design. The partitioning includes cutting one or more of the nets into cut nets and favoring the cutting of ones of the plurality of nets having a greater level of suitability over others of the plurality of nets having a lesser level of suitability. The design tool assigns each cut net to one group of a plurality of groups and inserts respective time-division multiplexing circuitry on each group of cut nets. The design toon then places the circuit design on the IC device.

Evaluation of nets for suitability of time domain multiplexing during partitioning and placing a circuit design

Processing a circuit design that specifies application logic and debugging logic includes partitioning the circuit design. Each partition includes a part of the application logic and a part of the debugging logic, each partition is specified for implementation on a respective IC die, and the circuit design specifies connections between a part of the application logic in one partition and a part of the debugging logic in another partition. The connections between the part of the application logic in the one partition and the part of the debugging logic in the other partition are changed to connections from the part of the application logic in the one partition to a part of the debugging logic in the one partition. The part of the application logic and the part of the debugging logic of each partition are placed and routed on the respective IC die.

Processing of a circuit design for debugging

Approaches for routing clock signals of a circuit design on an IC include determining initial partitions of clock sources and clock loads. Each initial partition includes one of the clock sources and a subset of the clock loads associated with the one clock source, and initial each partition defines an area of the IC in which the one of the clock sources and the associated subset of clock loads are placed. A processor determines for each of the initial partitions, whether or not the initial partition has a congested clock region. For each initial partition determined to have a congested clock region, the processor defines a respective new partition by excluding the one of the clock sources from the new partition. The new partition includes the subset of the clock loads and does not include the one clock source. The processor then routes clock signals from the clock sources to the clock loads.

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San Jose, CA, United States of America

Raoul Badaoui