Sun Microsystems, Inc.

Texas Instruments Corporation

Ampex Corporation

Raoul B Salem

Sathyanandan Rajivan

Raymond A Heald

E Ajith Amerasekera

Vinson R Perry

Wen-Jay Hsu

Waseem Ahmad

Vernon R Brethour

Subramanian Ganesan

An electronic assembly is described herein having a first semiconductor integrated circuit substrate with circuitry disposed thereon. This semiconductor integrated circuit substrate is coupled with a package through a first plurality of electrical connections. Sandwiched between portions of the semiconductor integrated circuit substrate and the package is an electronic assembly which is coupled to the semiconductor substrate circuitry and also the package through low resistance, low inductance connections. An electronic subassembly is described which includes a second semiconductor substrate having circuitry disposed thereon, the circuitry forming one or more of a capacitor, a charge pump, or a voltage regulator. Insulating material is disposed over the circuitry, and vias are formed therethrough. Metal bands are disposed to be continuous around the outside of the subassembly, thereby also forming a connection with the second semiconductor circuitry. The electronic subassembly metal bands then make connections with the circuitry of the semiconductor integrated circuit substrate and the package.

Electronic assembly having improved power supply bus voltage integrity

The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller. In turn, the tuning controller generates corresponding tuning pattern signals enabling target circuit(s) to changeably tune the target parameter by selectively enabling different tunable portions of the target circuit. For example, by selecting the appropriate load resistance and/or capacitance of the tunable circuit, the rise/fall time of the target circuit is tuned for compatibility with respect to the other portions of the IC or system. The tunable circuit of the present invention advantageously lends itself to post-fabrication correction of design or fabrication problems, thereby increasing the potential yield rate. In addition, the tunable circuit can be tested under different operating conditions in a non-destructive manner without the need for another time-consuming and costly IC fabrication cycle. Other advantages include the ability to selectively operate target circuit(s) of the IC at a higher speed under ideal conditions and at a lower speed under hostile conditions.

Parametric tuning of an integrated circuit after fabrication

Parametric tuning of an intergrated circuit after fabrication

A output driving circuit having an output driving element, an overshoot protection mechanism, and an undershoot protection mechanism. When the overshoot protection mechanism senses an overshoot voltage at the output terminal of the output driving element, it raises the voltage at the control terminal of the output driving element. This serves to maintain the voltage between the output terminal and the control terminal of the output driving element within a safe range, thereby preventing overstress or damage to the element. When the undershoot protection mechanism senses an undershoot voltage at the output terminal of the output driving element, it lowers the voltage at the control terminal of the output driving element. This serves to maintain the voltage between the output terminal and the control terminal of the output driving element within a safe range, which in turn prevents overstress and damage to the element. The output driving circuit also has a recovery circuit for accelerating the process of returning the output driving element to normal operation after the effects of overshoot and undershoot have ceased. This aids in accelerating the operation of the output driving circuit.

Output driver with overshoot and undershoot protection

Bias circuits which define control terminal voltages in a cascoded nMOS ESD protection circuit, such that the circuit is in high impedance state (OFF) during normal operation, and low impedance (ON) during an ESD event. G1 and G2 are the driver circuits which define V3 and V4 during an ESD event at the pad. During normal operation, V3 and/or V4 are high and no current flows between the pad and V.sub.SS. During an ESD event, V3 and V4 are high and both devices conduct MOS current as the lateral NPNs turn on. Diode D1 conducts current to charge C.sub.c, the chip capacitance, raising V.sub.DD, enabling G1 and G2 to turn on and raise V3 and V4 to levels greater than the nMOS threshold voltage.

Cascoded-MOS ESD protection circuits for mixed voltage chips

A method is provided for accurately determining the propagation delay of a gate under consideration in a static timing analyzer. This is accomplished by determining both the output load and input rise time of the gate under consideration. These values are then compared with a load versus rise time grid having previously determined values of propagation delay (points) for specified combinations of load and input rise time. These points are then used to interpolate a value of propagation delay for the gate under consideration by an interpolation technique that accounts for at least one of the following non-linear effects: the feed forward capacitance of a gate, soft switching, gate resistance, source and drain resistance, and/or other non-linear effects. The method accounts for each non-linear effect by imparting a corresponding component to propagation delay only in that range of output load and input rise time for which that non-linear effect is most pronounced.

Method of determining signal propagation delay through circuit elements

A circuit for suppressing the effects of excessive highlights is automatically enabled in response to highlights in the viewed scene which exceed a given threshold. The circuit is used in combination with a special pickup tube or tubes which include excessive highlight protection elements and a corresponding mode of operation. The circuit allows the continuous operation of the pickup tubes with improved resolution at a heretofore prohibitive, but preferred, high voltage level (e.g., 950 volts), rather than the generally accepted and recommended operating level (e.g., 750 volts) therefor, while prolonging the lifetime of such tubes. Detector means generates the circuit enable signal in response to the presence of highlights in excess of the given threshold. Control circuit means are conditioned thereby to drive the tube into the corresponding mode of operation during the line flyback period corresponding to the horizontal blanking interval.

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Redwood City, CA, United States of America

Raoul B Salem