Vlsi Technology, Inc.

Koninklijke Philips Corporation N.v.

Philips Electronics North America Corporation

Philips Semiconductor, Inc.

Nxp B.v.

Philips Semiconductors Inc.

Rao Venkateswara Annapragada

Milind Ganesh Weling

Subhas Bothra

Calvin T Gabriel

Samuel Vance Dunton

Tekle M Tafari

A method of improving adhesion of a cap oxide to nanoporous silica for integrated circuit fabrication. In one embodiment, the method comprises several steps. The first step is to receive a wafer in a deposition chamber. Then a porous layer of material is deposited on the wafer. Next, a portion of the porous layer is densified in order to make it more compatible for adhesion to a cap layer. Finally, a cap layer is deposited onto the porous layer.

Method of improving adhesion of cap oxide to nanoporous silica for integrated circuit fabrication

Disclosed is a method of making a reliable via hole in a semiconductor device layer, and a reliable via structure having internal wall surface layers that are hydrophobic, and thereby are non-moisture absorbing. The inner wall of the via structure has a layer of material having a characteristic of spin on glass (SOG), such that the characteristic is that the outer layer of the SOG oxidizes during photoresist ashing to form a surface layer of silicon dioxide in the via hole wall. In the method, the via structure is placed through a chemical dehydroxylation operation after the ashing operation, such that the layer of silicon dioxide in the via hole wall is converted into a hydrophobic material layer. The conversion is performed by introducing a halogen compound suitable for the chemical dehydroxylation operation, wherein the halogen compound may be NH F or CCl .

Reliable via structures having hydrophobic inner wall surfaces

A method of determining an end point for a remote microwave plasma cleaning system. In one embodiment, the method comprises several steps. The first step is to expose an electrical device to a deposition operation. Next, the electrical device is exposed to a plasma cleaning operation. In the following step, a value for a performance characteristic of the electrical device is measured. In the last step, an amount of cleaning performed on the electrical device is calculated based on a relationship between a baseline value of the performance characteristic and on the measured value of the performance characteristic of the electrical device.

Method of determining an end point for a remote microwave plasma cleaning system

A method of manufacturing semiconductors is provided which avoids metal deposition in voids formed in the dielectric between interconnects. In a preferred embodiment, an etch stop recess portion is provided over the dielectric which encloses the interconnects to prevent via openings from extending into the voids during the etching of the via openings. Accordingly, metal deposition of the voids during metal deposition of the vias is avoided. As a result, the semiconductors so formed has reduced capacitance between the interconnects and improved reliability since the voids are cleared of any metal deposition.

Method for reducing the capacitance between interconnects by forming voids in dielectric material

A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas. Specifically, one embodiment of the present invention utilizes a dry abrasive polishing pad to abrade the desired surface of the semiconductor wafer within a vacuum planarization chamber. As a result of abrading the surface, the abrasive polishing pad breaks the chemical bonds of a thin layer of the dielectric surface material. Once the chemical bonds are broken, reactive radicals within a plasma gas chemically react with the surface material thereby forming a gaseous species which is highly volatile. In other words, the plasma gas is used to remove previously mechanically polished material from the dielectric layer. Subsequently, the newly formed gaseous species is removed from the vacuum planarization chamber. This process of removing material from the surface of the semiconductor wafer continues until the surface is sufficiently planarized. In this manner, the present invention provides a dry process for planarizing a surface of a semiconductor wafer.

Gas phase planarization process for semiconductor wafers

A method for depositing a liner dielectric on a semiconductor substrate provides for sufficient adhesion of low dielectric constant spin-on materials among metal layers in sub-micron processes. In an example embodiment, a method for adhering MSQ provides for a liner oxide on an aluminum alloy layer on a semiconductor substrate. First, the substrate is placed into a PECVD environment. A gas mixture of trimethylsilane and N,O is introduced into the PECVD environment at a trimethylsilane-to-N,O ratio of about 1:20 to 1:30. The gas mixture is reacted to deposit an oxide liner of a predetermined thickness. Adjusting the gas mixture trimethylsilane-to-N,O ratio to about 1:3 to 1:7 over the course of about 5 to 20 seconds, and sustaining the reaction thereof, deposits a methyl doped oxide.

Method and structure for adhering MSQ material to liner oxide

A method for making a multi-layered integrated circuit structure, includes depositing a methyl compound spin on glass layer over a substrate. The spin on glass layer is treated by plasma-deposition to form a SiO,skin on the methyl compound spin on glass layer and then treated again by plasma-deposition to form a cap layer which adheres to the SiO,skin.

Process to improve adhesion of PECVD cap layers in integrated circuits

A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas.

A method for fabricating inter-metal oxide in semiconductor devices and semiconductor devices is provided. The method begins by providing a semiconductor substrate having a plurality of patterned conductive features. The method then moves to where a high density plasma (HDP) operation is performed and is configured to deposit an oxide layer over the plurality of patterned conductive features. The HDP operation includes a deposition component and a sputtering component. The deposition component is driven by a deposition gas and the sputtering component is driven by a sputtering gas. The HDP operation forms oxide pyramids over the plurality of patterned conductive features. The method now moves to where the deposition gas is removed to close off the deposition component in the HDP operation. Now, the HDP operation is run with the sputtering gas while retaining the sputtering component. The sputtering component is configured to substantially remove the oxide pyramids from over the plurality of patterned conductive features. Preferably, the plurality of patterned conductive features are either patterned metallization features or patterned polysilicon features.

Semiconductor dielectric structure and method for making the same

A method for making a multi-layered integrated circuit structure, includes depositing a methyl doped silicon oxide layer over a substrate. SiO,skin is deposited on the methyl doped silicon oxide layer by decreasing the flow of CH,SiH,, increasing the flow of SiH,and keeping the flow of H,O,constant for a period of time. Finally, a cap layer is deposited which adheres to the SiO,skin.

Process to improve adhesion of cap layers in intergrated circuits

Disclosed is a method of making a reliable via hole in a semiconductor device layer, and a reliable via structure having internal wall surface layers that are hydrophobic, and thereby are non-moisture absorbing. The inner wall of the via structure has a layer of material having a characteristic of spin on glass (SOG), such that the characteristic is that the outer layer of the SOG oxidizes during photoresist ashing to form a surface layer of silicon dioxide in the via hole wall. In the method, the via structure is placed through a chemical dehydroxylation operation after the ashing operation, such that the layer of silicon dioxide in the via hole wall is converted into a hydrophobic material layer. The conversion is performed by introducing a halogen compound suitable for the chemical hydroxilation operation, wherein the halogen compound may be NH.sub.4 F or CCl.sub.4.

Methods for making reliable via structures having hydrophobic inner wall

A semiconductor device has a device layer, a conductive structure, such as a conductive line, disposed over the device layer, and a porous dielectric layer disposed over the device layer and the conductive structure. At least one via is formed through the porous dielectric layer to the conductive structure with a second dielectric material formed along sidewalls of the via. Often, the porous dielectric layer includes a hydrophobic aerogel material having silicon-hydrogen bonds. One exemplary method of making the semiconductor device includes forming a conductive structure over a device layer of the semiconductor device and then forming a porous dielectric layer over the device layer and the conductive structure. A first via is formed through the porous dielectric layer to the conductive structure. The first via is filled with a second dielectric material that is less porous than the porous dielectric layer and then a second via is formed through the second dielectric material to the conductive structure.

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San Jose, CA, United States of America

Rao Venkateswara Annapragada