Intel Corporation

Ranjul Balakrishnan

Navneet Kumar Singh

Shanto A Thomas

Bok Eng Cheah

Jackson Chung Peng Kong

Arvind Sundaram

Prabhat Ranjan

Ramaswamy Parthasarathy

Stephen H Hall, Jr

Shailendra Singh Chauhan

Raghavendra Ramesh Rao

Vikas Mishra

Roman Meltser

Geejagaaru Krishnamurthy Sandesh

Long Wang

Sandesh G Krishnamurthy

Jackson Cp Kong

Shivani R Jain

Yogasundaram Chandiran

Sandesh Krishnamurthy Geejagaaru

Pradeep Ramesh

Technologies for shielding an inductor on a circuit board are disclosed. In the illustrative embodiments, a circuit board has a voltage regulator on top of it and one or more signal traces routed beneath or near the voltage regulator. Partial metal vias are positioned between the signal traces and the voltage regulator. The partial metal vias extend from one trace layer of a circuit board towards another trace layer, but the partial metal vias do not connect the two trace layers. The partial metal vias partially shield the signal traces from noise caused by the voltage regulator.

Technologies for shielding an inductor on a circuit board

Apparatus and methods employing twisted differential compensation for routing high-speed signals near power delivery inductors. Traces used for a high-speed differential signal including a P trace and an N trace are routed through one or more layers in a multi-layer printed circuit board (PCB) substrate and employ a twisted portion proximate to the centerline of an inductor under which portions of the P and N traces are swapped horizontally in a layer parallel to the top plane and/or are swapped vertically by swapping layers. The signal paths are routed such that a level of noise inductively coupled into the P trace and the N trace from the inductor is approximately equally. Stripline structures are used for signals that are routed under an inductor, while stripline and microstrip structures are used for signals routed adjacent to an inductor.

Twisted differential compensation for routing high-speed signals near power delivery inductors and system miniaturization

A memory module has pads on the top and bottom surfaces of a module printed circuit board (PCB). The pads match the pin layout of one or more memory devices to be mounted on the memory module. The pads on one surface of the PCB electrically interconnect to the memory device(s), and the pads on the other surface electrically interconnect to pads on a system board, such as a motherboard. With the pad layout on the memory module, the pad layout of the system board can be the same for a memory-down implementation and for a removable memory module. The pad layout provides good signal-to-noise performance and can enable a memory module for low power double data rate (LPDDR) memory, double data rate (DDR) memory, and graphics double data rate (GDDR) memory.

Low profile SODIMM (small outline dual inline memory module)

In one embodiment, an apparatus includes a circuit board having a parallel bus with a first trace and a second trace, a first inductive coil coupled to the first trace, and a second inductive coil coupled to the second trace. The first and second inductive coils are arranged to inductively couple with one another to reduce cross talk effects in the parallel bus.

Inductive coupling structures for reducing cross talk effects in parallel bus technologies

A PCB having a first surface and a second surface includes a trench extending through the PCB, a plurality of conductive traces on one or more sidewalls of the trench. The plurality of conductive traces extends through the PCB and may be arranged in pairs across from one another along at least a portion of the length of the trench. A first set of conductive contacts are arranged in a first zig-zag pattern around a perimeter of the trench. A second set of conductive contacts are arranged in a second zig-zag pattern around the perimeter of the trench. In some cases, the first and second zig-zag patterns are arranged with respect to one another around the perimeter of the trench in an alternating fashion. A chip package is also disclosed having a pin arrangement that couples to the corresponding arrangement of conductive contacts on the PCB.

Chip package with staggered pin pattern

For circuit boards that may be used in computing devices, a horizontal inductor, or an array of such inductors, may be coupled to a circuit board having a plurality of signal routing lines in a second layer from a surface of the circuit board and the horizontal inductor is positioned over these signal routing lines and may generate magnetic field lines that directionally follow the signal routing lines. The horizontal inductor may have a coiled wire with a central axis that is oriented horizontally with the surface of the circuit board. The horizontal inductor, or an array of such inductors, may be coupled to a support board attached to the circuit board.

Inductor array and support

Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board,

Methods of forming package structures for enhanced memory capacity and structures formed thereby

A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in electronic communication with at least one second microelectronic device through the microelectronic interposer which positions the at least one second microelectronic device outside a periphery of the first microelectronic device. The microelectronic interposer may further include at least one recess for achieving a desired height and/or enabling various configurations for the microelectronic package.

Microelectronic interposer for a microelectronic package

Embodiments of the present disclosure provide techniques and configurations for a cable assembly for single wire communications (SWC). In one instance, the cable assembly may comprise a wire having a wire end to couple with a signal launcher of an electronic device, and a first cover portion to house a first portion of the wire that extends from the wire end. The first cover portion may comprise a shape to conform to a shape of the signal launcher, and may be fabricated of a material with a dielectric constant above a threshold. The assembly may further comprise a second cover portion coupled with the first cover portion to house a second portion of the wire that extends from the first wire portion and protrudes from the first cover portion. The second cover portion may be fabricated of a ferrite material. Other embodiments may be described and/or claimed.

Cable assembly comprising a single wire coupled to a signal launcher and housed in a first cover portion and in a second ferrite cover portion

Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.

Growing community of inventors

Bengaluru, India

Ranjul Balakrishnan