Taiwan Semiconductor Manufacturing Comp. Ltd.

Ranjith Kumar

Mohammed Rabiul Islam

Kumar Lalgudi

Jianyang Xu

A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.

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Hsinchu, Taiwan

Ranjith Kumar