Texas Instruments Corporation

Texax Instruments Incorporated

Ranjit Gharpurey

Anuj Batra

Anand Ganesh Dabak

Heng-Chih Lin

Jaiganesh Balakrishnan

Paul H Fontaine

Paul Aymeric Fontaine

Gugliemo Sirna

Abdellatif Bellaouar

Naveen Krishna Yanduru

Sridhar Ramaswamy

William J Bright

Petteri Matti Litmanen

Francesco Dantoni

Snehamay Sinha

Paul C Yu

Feng Chen

Shereef Shehata

Chien-Chung Chen

Michel Frechette

Gopalarao Kadamati

A PHY entity for a UWB system utilizes the unlicensed 3.1-10.6 GHZ UWB band, as regulated in the United States by the Code of Federal Regulation, Title 47, Section 15. The UWB system provides a wireless pico area network (PAN) with data payload communication capabilities of 55, 80, 110, 160, 200, 320 and 480 Mb/s. The UWB system employs orthogonal frequency division multiplexing (OFDM) and uses a total of 122 sub-carriers that are modulated using quadrature phase shift keying (QPSK). Forward error correction coding (convolutional coding) is used with a coding rate of 11/32, 1/2, 5/8 and 3/4.

Time-frequency interleaved orthogonal frequency division multiplexing ultra wide band physical layer

A radio such as a frequency division duplex (FDD) radio () has a first local oscillator (LOI and LOQ) that is set to coincide with the transmitter section's () center frequency or a sub-harmonic thereof. In this way, after the first down-conversion, the transmit interferer is converted to DC, where it can be effectively removed using a simple high-pass filter () such as a DC blocking capacitor. Image rejection is achieved by the use of a two-step down-conversion approach that uses quadrature local oscillators to implement a single-sideband down-converter.

Radio architecture for use with frequency division duplexed systems

System for ultra-wideband communications providing high data rates over an extended operating range in the presence of interferers. A preferred embodiment comprises an ultra-wideband (UWB) device that makes use of a portion of the UWB frequency range to help provide good performance in the presence of interferers. Additionally, since only a portion of the UWB frequency range is used, multiple devices can simultaneously transmit and receive by using different portions of the UWB frequency range.

Ultra-wideband communications system devices

System and method for maximizing a signal strength of a received signal pulse. A preferred embodiment comprises a self-adjusting correlator/integrator (for example, correlator/integrator) that uses no historical timing information. The self-adjusting correlator/integrator uses a plurality of simple correlators/integrators (for example, correlator/integrator) which are configured to process a received signal at various times surrounding the signal pulse's expected arrival. A comparator (for example, comparator) selects an output of the simple correlators/integrators with greatest magnitude.

Ultra-wideband (UWB) receiver

System and method for combining maximizing a received signal in a multipath environment. A preferred embodiment comprises a rake receiver (for example, rake receiver), created from switched capacitors, with N fingers. Each of the fingers is coupled to a signal input for a period of time to accumulate a charge on a storing capacitor (for example, storing capacitor). The charges stored on the storing capacitors can then be read-out to produce a value. The rake receiver can implement either equal ratio combining or maximum gain combining to further improve received signal strength.

Rake receiver architecture for an ultra-wideband (UWB) receiver

A system and method implement very high data rate baseband DACs suitable for wireless applications related to new standards (e.g. Ultra-Wide Band) using CMOS processes allowing an integrated solution with the deep-submicron CMOS digital baseband. A single CMOS block working at full speed is discarded in favor of several blocks, each working at a fraction of the original data rate.

Digital-to-analog converter data rate reduction by interleaving and recombination through mixer switching

A circuit provides a reduced harmonic content output signal OUTA and/or OUTB that is modulated according to an input signal. The circuit has an oscillator circuitand a harmonic rejection mixer (HRM). The oscillator circuitincludes at least one 'circuit portion' (FIG.A) configured to receive first and second orthogonal oscillator input signals (two of I, I&#x2212;, Q, Q&#x2212;) having respective first and second phases, and to provide an arbitrarily large number of oscillator output signals (&#x3c6;M) having respective mutually distinct phases that are interpolated between the first and second phases. Harmonic rejection mixeris configured to use the input signal to modulate a combination of the oscillator output signals, the oscillator output signals being respectively weighted so as to provide an emulated sinusoidal signal constituting the reduced harmonic content output signal.

Current interpolation in multi-phase local oscillator for use with harmonic rejection mixer

A current-domain transmitter is configured to receive an input signal and provide a transmitted signal. The transmitter has a plurality of elements, operatively arranged between the input signal and the transmitted signal and configured to represent the input signal with respective electric currents whose respective current magnitudes are each substantially proportional to the input signal. The elements may include a current-steering digital-to-analog converter (DAC), a current mode filter (such as an LPF), a current mode mixer, and/or a current mode amplifier.

Current mode transmitter

A speed-up mode control system is operative to generate a speed-up mode signal based on a gain control signal from associated digital circuitry. The speed-up mode signal controls electronics associated with one or more amplifiers to facilitate settling time of an output signal of the amplifier(s) that occurs when the gain of the amplifier changes. The gain control signal also can be delayed to provide a delayed version of the gain control signal for controlling gain of the amplifier(s).

Speed-up mode implementation for direct conversion receiver

System and method for analog signal generation and manipulation in an ultra-wideband (UWB) transmitter. A preferred embodiment comprises a digital portionof an UWB transmitter (for example, transmitter), which is responsible for encoding a data stream to be transmitted, and an analog portion. The analog portioncreates a stream of short duration pulses from the encoded data stream and then filters the stream of short duration pulses. To simplify the generation of the short duration pulses, a quantized representation of the short duration pulse is used. The quantized representation is created via the use of control signals that by coupling differential amplifiers together (such as amplifier), generate a voltage drop across a resistor (such as resistor) and hence, a current.

Ultra wideband (UWB) transmitter architecture

The mixer circuit includes a differential rf input driver; a differential local oscillator input circuit coupled to the differential rf input driver; a non-linear load coupled to the differential local oscillator input circuit wherein the non-linear load compensates for non-linearity of the differential rf input driver. The non-linear load has a V-I (voltage-current) transfer function the inverse of the input driver. This improves the mixer linearity without sacrificing the Gain or Noise Figure.

Inverse function method for semiconductor mixer linearity enhancement

The present invention pertains to a MOS type differential buffer circuit. The buffer proposed herein utilizes capacitive coupling to apply small AC signals to an amplifying current source to mitigate attenuation owing to body effect and output impedance, among other things, in an associated follower component. The proposed circuit does not, however, promote an increase in current and/or power dissipation. Additionally, the circuit allows a desired gain to be achieved while maintaining a relatively constant output impedance, compared to a simple differential source follower.

CMOS differential buffer circuit

The circuit with adaptive amplifier output common mode voltage adjustment includes: a differential pre-amplifier; a re-generated comparator having a differential input coupled to a differential output of the pre-amplifier; and a replica comparator coupled to a common mode node of the pre-amplifier for adjusting a common mode of the pre-amplifier. The replica comparator provides a trip-point reference to set the output common mode of the pre-amplifier. This sets the output common mode of the pre-amplifier to the most sensitive region of the re-generated comparator.

Adaptive amplifier output common mode voltage adjustment

Configuring an analog-to-digital converter includes receiving a control signal and an input analog signal at an analog-to-digital converter, where the control signal has either a first state or a second state. The first state is associated with a first configuration and the second state is associated with a second configuration. If the control signal has the first state, the analog-to-digital-converter is configured in the first configuration and a digital signal comprising a first digital signal is generated according to a pipeline conversion. If the control signal has the second state the analog-to-digital converter is configured in the second configuration and the digital signal comprising a second digital signal is generated according to a multi-stage sigma delta modulation conversion. The digital signal is processed to yield a digital output.

Reconfigurable analog-to-digital converter

A technique for generating carrier frequencies with fast hopping capability associated with multiband systems for ultra wideband applications. The technique employs a single VCOthat is locked in a PLL. The output of this VCOis divided in the frequency domain. The divided frequencies thus obtained are combined in a single-sideband manner to obtain various other frequencies. The single-sideband combination requires open loop operations such as multiplication and addition or subtraction to implement, and hence is very fast. The VCO center frequency is not disturbed in the process. Since the required frequencies are generated in an open-loop fashion, instead of inside a PLL, the speed is increased by orders of magnitude.

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Ann Arbor, MI, United States of America

Ranjit Gharpurey