Advanced Micro Devices Corporation

Microsoft Technology Licensing, LLC

Globalfoundries Inc.

Ranjit Gannamani

Jun Zhai

Zhen Zhang

Mohammad A Khan

Brian K Langendorf

Amit P Marathe

Frank G Kuechenmeister

Raj N Master

Michael Zhouying Su

Kingsuk Maitra

Xia Li

Tung Thanh Nguyen

Jaime Bravo

Rune Hartung Jensen

Julia Purtell

Kevin W Lim

Srinivasan Parthasarathy

Embodiments are disclosed that relate to implementing semiconductor device cooling systems that leverage awareness of regional voltage and temperature reliability risk considerations. For example, one disclosed embodiment provides a method of implementing a cooling system configured to cool an integrated circuit. The method involves first determining a heat dissipation factor that would reduce each region of the integrated circuit to a reduced temperature in order to maintain an overall failure rate. An analysis is then performed, using an insight about the relative reliability risk of elevated voltage and temperatures, to identify a region of the integrated circuit whose temperature can be permitted to rise without exceeding the overall failure rate, thereby permitting implementation of a cooling system with a reduced heat dissipation factor.

Reliability aware thermal design

Methods are provided for packaging a semiconductor die having a first surface. In accordance with an exemplary embodiment, a method comprises the steps of forming a trench in the first surface of the die, electrically and physically coupling the die to a packaging substrate, forming a sealant layer on the first surface of the die, forming an engagement structure within the trench, and infusing underfill between the sealant layer and the engagement structure and the packaging substrate.

Semiconductor device having a filled trench structure and methods for fabricating the same

Various semiconductor chip arrangements and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip that has an external peripheral wall to a first side of a substrate. A first metallic ring is coupled to the first side of the substrate. The first metallic ring has an internal peripheral wall that frames the semiconductor chip and is separated from the external peripheral wall by a gap. The first metallic ring has a coefficient of thermal expansion less than about 6.0 10K.

Semiconductor chip with solder joint protection ring

Various semiconductor chip underfills and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate to leave a gap therebetween, and forming an underfill layer in the gap. The underfill layer includes a first plurality of filler particles that have a first average size and a second plurality of filler particles that have a second average size smaller than the first average size such that the first plurality of filler particles is concentrated proximate the substrate and the second plurality of filler particles is concentrated proximate the semiconductor chip so that a bulk modulus of the underfill layer is larger proximate the substrate than proximate the semiconductor chip.

Semiconductor chip with stratified underfill

A system and method for decapsulating a chip-scale package having a first width are disclosed. The method and system include coupling the chip-scale package to a substantially rigid receptacle. The receptacle has a second width and a periphery. The second width is larger than the first width. The chip-scale package does not extend to the periphery of the receptacle. The method and system further include holding the receptacle in proximity to the periphery and decapsulating the chip-scale package.

Method and system for providing a package for decapsulating a chip-scale package

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San Jose, CA, United States of America

Ranjit Gannamani