Intel Corporation

Ranjeet Alexis

Robert E Larsen

Mickey L Fandrich

Sanjay S Talreja

Mamun Ur Rashid

Peter K Hazen

Charles W Brown

Salim B Fedel

Rodney R Rozman

Richard J Durante

Harry Q Pon

Marcus E Landgraf

A read-while-write memory device. The read-while-write memory device includes a read memory plane and a write memory plane. A first number of read sense amplifiers greater than one is coupled in parallel to the read memory plane in response to a memory read operation. A second number of verify sense amplifiers greater than zero and less than the first number is coupled to the write memory plane in response to one of a memory write or erase operation.

Read-while-write memory including fewer verify sense amplifiers than read sense amplifiers

An interface for a read-while-write memory. A memory device includes a single-chip memory array and an interface that is responsive to one or more commands to configure the memory array in a read-while-write configuration.

Method and apparatus for placing a memory in a read-while-write mode

A method and apparatus for partitioning a flash memory device is provided. The flash memory device includes a plurality of partitions, each partition able to be read, written, or erased simultaneously with the other partitions.

Flash memory partitioning for read-while-write operation

A low-power interface for nonvolatile writeable memory is described. The interface includes an input buffer and an output buffer. The input buffer receives input signals having one of a number of pairs of logic levels. The input buffer is coupled to the nonvolatile writeable memory and coupled to the same power supply as the nonvolatile writeable memory. The input buffer translates the input signals received to the signal level used by the nonvolatile writeable memory. The output buffer is coupled to the nonvolatile writeable memory and is coupled to a different power supply from the input buffer and the nonvolatile writeable memory. The output buffer translates the signals received from the nonvolatile writeable memory to the same signal levels as the input signal. The input buffer and output buffer utilize input/output signals having logic levels compatible with complementary metal-oxide semiconductor (CMOS) technology.

Self-configuring interface architecture on flash memories

A self-compensating current mirroring circuit including first and second transistor devices respectively joined in the path of a current to be mirrored and the path of a mirrored current, the first transistor device being in circuit with a compensating transistor device, the sizes of the first and second transistor devices being such that the currents through the first and second transistor devices are maintained at identical levels during operation.

Self-compensating geometry-adjusted current mirroring circuitry

A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.

Special test modes for a page buffer shared resource in a memory device

A memory device includes a cell array having a plurality of memory cells and a read/write circuit having circuitry for selecting, writing, and reading the memory cells according to a plurality of control signals. A control register circuit is provided that has at least one control register coupled to communicate over a central control bus. A control access circuit is provided that receives an access request targeted for the control register, and translates the access request into an access cycle on the central control bus. The access cycle loads the control register and causes the control register circuit to generate the control signals. The control access circuit receives the access request targeted for the control register from an array controller circuit that generates the access request to load the control register and generate the control signals according to a user command received over a host bus. The control register includes an address decode circuit, a function decode circuit, a master data latch, a slave data latch, and a read control circuit.

Memory device with a central control bus and a control access register

A circuit for rapidly raising the value of voltage at a circuit node to a predetermined precise level including first and second charging circuits, and circuitry including a timing circuit responsive to an enabling signal for connecting the one of the charging circuits to the circuit node for a first limited period and then connecting the other of the charging circuits to the circuit node thereafter.

Method and apparatus for improving power up time of flash eeprom memory

A current mirroring circuit including first and second field effect transistor devices connected in a current mirroring arrangement, a circuit for summing a first plurality of identical currents to provide current for the first field effect transistor device, a circuit for dividing the current from the second field effect transistor device into a second plurality of identical currents, and an output circuit connected to mirror any one of the second plurality of identical currents.

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Folsom, CA, United States of America

Ranjeet Alexis