Globalfoundries Singapore Pte. Ltd.

Georgia Tech Research Corporation

Agency for Science, Technology and Research

National University of Singapore

Illinois Tool Works Inc.

Ranjan Rajoo

Kai Chong Chan

Juan Boon Tan

Frank G Kuechenmeister

Ramasamy Chockalingam

Dirk Breuer

Xiaodong Li

Ee Hua Wong

Xuesong Rao

Mahadevan Krishna Iyer

Venkata Narayana Rao Vanukuru

Chee Kong Leong

Kuo Tsing Tsai

Wai Kwan Wong

Poi Siong Teo

The present disclosure relates to semiconductor structures, and more particularly, to crackstop structures and methods of manufacture. The structure includes: a die matrix comprising a plurality of dies separated by at least one scribe lane; and a crackstop structure comprising at least one line within the at least one scribe lane between adjacent dies of the plurality of dies.

Crackstop structures

The embodiments herein relate to packages of semiconductor devices having a shielding element and methods of forming the same. An assembly is provided. The assembly includes a semiconductor chip having a passive component and a package within which the semiconductor chip is positioned in. The package includes a shielding element and a package conductive component, and the package conductive component is electrically coupled with the passive component of the semiconductor chip.

Shielding elements for packages of semiconductor devices

A semiconductor device is provided that includes a bond pad, an insulating layer, and a bonding structure. The bond pad is in a dielectric layer and the insulating layer is over the bond pad; the insulating layer having an opening over the bond pad formed therein. The bonding structure electrically couples the bond pad in the opening. The bonding structure has a height that at least extends to an upper surface of the insulating layer.

Bonding structures of semiconductor devices

A semiconductor device is provided that includes a dielectric layer, a bond pad, a passivation layer and a planar barrier. The bond pad is positioned in the dielectric layer. The passivation layer is positioned over the dielectric layer and has an opening over the bond pad. The planar barrier is positioned on the bond pad.

Bond pads of semiconductor devices

A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing a wafer stack with first and second wafers bonded together. The wafers include edge and non-edge regions, and at least one of the first and second wafers includes devices formed in the non-edge region. The first wafer serves as the base wafer while the second wafer serves as the top wafer of the wafer stack, where the base wafer is wider than the top wafer, providing a step edge of the wafer stack. An edge protection seal is formed on the wafer stack, where first and second layers are deposited on the wafer stack including at the top wafer and step edge of the wafer stack. The portion of the first and second layers on the step edge of the wafer stack forms the edge protection seal which protects the devices in the wafer stack in subsequent processing.

Wafer stack protection seal

Semiconductor devices and methods of forming a semiconductor device are disclosed. The device includes a wafer with top and bottom surfaces. The wafer includes edge and non-edge regions. The wafer includes a plurality of devices and partially processed TSV contacts disposed in the non-edge region and a groove disposed at the edge region. The groove enables edges of the wafer to be automatically trimmed off as the wafer is subject to a back-grinding planarization process to expose the TSV contacts in the non-edge region of the wafer.

Edge structure for backgrinding asymmetrical bonded wafer

A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing first and second wafers with top and bottom surfaces. The wafers include edge and non-edge regions, and the first wafer includes devices formed in the non-edge region. A first protection seal may be formed at the edge region of the first wafer. The first and second wafers may further be bonded to form a device stack. The protection seal in the device stack contacts the first and second wafers to form a seal, and protects the devices in subsequent processing.

A method and device to elongate a solder joint are provided. The method begins by forming an elongator on a first substrate. The elongator comprises an expander and an encapsulant to encapsulate the expander. A solder joint is formed to connect the first substrate to a second substrate. Thereafter, the encapsulant is softened to release the expander from a compressed state to elongate the solder joint. The device to elongate a solder joint comprises a substrate having an elongator formed on it. The elongator includes an expander in a compressed state and an encapsulant to encapsulate the expander.

Method and device to elongate a solder joint

We disclose a technique to generate stretched solder columns (bumps) at the wafer level, suitable for wafer level packaging. This is accomplished through use of using two wafers&#x2014;the standard (functional) wafer that contains the integrated circuits and a master (dummy) wafer on whose surface is provided an array of solder bumps that is the mirror image of that on the functional wafer. After suitable alignment, both sets of solder bumps are melted and then slowly brought together till they merge. Then, as they cool, they are slowly pulled apart thereby stretching the merged solder columns. Once the latter have fully solidified, they are separated from the master wafer only.

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Singapore, Singapore

Ranjan Rajoo