Intel Corporation

Rangeen Basu Roy Chowdhury

Gautham N Chinya

Julien Sebot

Cristiano L Pereira

Ethan Schuchman

Jason M Agron

Girish Venkatasubramanian

Manjunath Shevgoor

Eric Kwesi Donkoh

Stephen J Tarsa

Rustam Miftakhutdinov

Sofia Pediaditaki

Vineeth Thamarassery Mekkat

Sebastian Christoph Albert Winkel

An apparatus comprises decoder circuitry to decode an instruction that includes an opcode to indicate a protected load operation, a source field for source memory address information, and a destination field to identify a destination register. The apparatus also comprises memory to store an allocate load-protect (LP) data structure with an entry for the identified destination register. The entry comprises an IP field and a status field. The apparatus also comprises load elision circuitry to (a) use the allocate LP data structure to determine whether the identified destination register has active status for the IP; (b) in response to determining that the identified destination register has active status for the IP, cause the instruction to be elided; and (c) in response to determining that the identified destination register does not have active status for the IP, cause the instruction to be executed. Other embodiments are described and claimed.

Systems, methods and apparatus for speculative elimination of load instruction

A processor comprising an instruction execution circuit to execute a second code stored at a second address of a memory, wherein the second code is translated from a first code stored at a first address of the memory and a translation table (TT) controller coupled to a translation table to store a TT entry comprising a mapping between the first address and the second address and an attribute field comprising an attribute value associated with execution of the second code, wherein the TT controller is to monitor execution of the second code by the instruction execution circuit and update, based on a performance metric of the execution, the attribute value of the TT entry.

Management of the untranslated to translated code steering logic in a dynamic binary translation based processor

A system on a chip is described that comprises a processor and a set of memory components that store instructions, which when executed by the processor cause the system on a chip to: generate, by a set of data collectors of a telemetry subsystem, a set of streams of telemetry metadata describing operation of the processor, forward one or more streams of telemetry metadata from the set of streams of telemetry metadata to a set of machine learning-driven adaptation decision models, receive, from the set of machine learning-driven adaptation decision models, a set of configuration parameters for controlling operation of the processor based on the one or more streams of telemetry metadata, and modify operation of the processor based on the set of configuration parameters.

Reducing microprocessor power with minimal performance impact by dynamically adapting runtime operating configurations using machine learning

Embodiments of apparatuses, methods, and systems for inter-cluster communication of live-in register values are described. In an embodiment, a processor includes a plurality of execution clusters. The processor also includes a cache memory in which to store a value to be produced by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters. The cache memory is separate from a system memory hierarchy and a register set of the processor.

Inter-cluster communication of live-in register values

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Santa Clara, CA, United States of America

Rangeen Basu Roy Chowdhury