Tensilica, Inc.

Cadence Design Systems, Inc.

Rangarajan Srinivasan

Earl A Killian

Dror E Maydan

David W Goodwin

Walter David Lichtenstein

Ricardo E Gonzalez

Albert Ren-Rui Wang

Pavlos Konas

Christopher Mark Songer

Akilesh Parameswar

Richard Ruddell

Nupur Bhattacharyya

Marines Puig Medina

Hongbin Ji

A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Automated processor generation system and method for designing a configurable processor

Automated processor generation system for designing a configurable processor and method for the same

A novel compression method uses bitmaps to reduce the memory storage requirement of routing table information to about 3 MB. The data structure can be used for both route lookup and update. It does not require a separate data structure to be used for route update. A fast route lookup method is also disclosed. An efficient update method supports incremental route update. Through configuring a processor properly and developing a few customized instructions specifically for route lookup, the system can achieve more than 10 million lookups per second (MLPS) at 200 MHz. Using a configurable processor for route lookup/update provides more flexibility and extensibility which supports different data structures and lookup/update methods to meet application specific needs. The data structure and lookup method can be implemented in pure hardware in a pipelined fashion to achieve approximately 100 MLPS.

Fast IP route lookup with configurable processor and compressed routing table

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Los Gatos, CA, United States of America

Rangarajan Srinivasan