Agency for Science, Technology and Research

Institute of Microelectronics

Other

Globalfoundries Singapore Pte. Ltd.

Vanguard International Semiconductor Singapore Pte. Ltd.

Vanguard Iniernational Semiconductor Singapore Pte. Ltd.

Ranganathan Nagarajan

Uppili Sridhar

Vaidyanathan Kripesh

Rakesh Kumar

Jia Jie Xia

Narayanan Balasubramanian

Yubo Miao

Bevita Kallupalathinkal Chandran

Chirayarikathuveedu Premachandran Sankarapillai

Seung Uk Yoon

Mahadevan Krishna Iyer

Ganesh Vetrivel Periasamy

Mihai Dragos Rotaru

Patrick Guo Qiang Lo

Wei Yip Loh

Mohanraj Soundarapandian

Yu Jau Chen

Quanbo Zou

Lakshmi Kanta Bera

Janak Singh

Shajan Mathew

Beng Yeung Ho

Vivek Chidambaram

Ling Xie

Chirayarikathuveedu Sankarapillai Premachandran

Bangtao Chen

Yung Chii Liang

Damaruganath Pinjala

Ren Chang Hong

Miles Jacob Gehm

Hengyun Zhang

Qinxin Zhang

Zhang Qingxin

Yu Bo Miao

Yi Su

Cai Jun

A method of forming a MEMS device includes providing a substrate having a device stopper. The device stopper is integral to the substrate and formed of the substrate material. A thermal dielectric isolation layer may be arranged over the device stopper and the substrate. A device cavity may be formed in the substrate and the thermal dielectric isolation layer. The thermal dielectric isolation layer and the device stopper at least partially surround the device cavity. An active device layer may be formed over the thermal dielectric isolation layer and the device cavity.

MEMS devices and methods of forming thereof

In a non-limiting embodiment, a device may include a substrate, and a hybrid active structure disposed over the substrate. The hybrid active structure may include an anchor region and a free region. The hybrid active structure may be connected to the substrate at least at the anchor region. The anchor region may include at least a segment of a piezoelectric stack portion. The piezoelectric stack portion may include a first electrode layer, a piezoelectric layer over the first electrode layer, and a second electrode layer over the piezoelectric layer. The free region may include at least a segment of a mechanical portion. The piezoelectric stack portion may overlap the mechanical portion at edges of the piezoelectric stack portion.

Piezoelectric MEMS devices and methods of forming thereof

In a non-limiting embodiment, a MEMS device may include a substrate having a device stopper. The device stopper may be integral to the substrate and formed of the substrate material. A thermal dielectric isolation layer may be arranged over the device stopper and the substrate. A device cavity may extend through the substrate and the thermal dielectric isolation layer. The thermal dielectric isolation layer and the device stopper at least partially surround the device cavity. An active device layer may be arranged over the thermal dielectric isolation layer and the device cavity.

The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a getter layer and further comprises a sacrificial layer. The wafer level package may be used in microelectromechanical systems (MEMS) packaging at a vacuum level of about 10 mTorr or less such as close to 1 mTorr (i.e. MEMS vacuum packaging).

Layer arrangement and a wafer level package comprising the layer arrangement

A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.

Fully salicided (FUCA) MOSFET structure

A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.

RF and MMIC stackable micro-modules

A substrate having target transfer regions thereon is provided. A sacrificial wafer is coated with a polymer layer with low adhesion to metals. A conductive layer is coated on the polymer layer and covered with a photoresist layer which is patterned to provide openings to the conductive layer. Thin film and passive or active device structures are formed on the conductive layer within the openings. The substrate is bonded to the sacrificial wafer wherein the thin film and passive or active device structures and the photoresist layer provide the bonding and wherein the thin film and passive or active device structures contact the substrate at the target transfer regions. The photoresist is stripped in a high frequency agitation bath wherein the photoresist separates from the sacrificial wafer and wherein the thin film and passive or active device structures separate from the polymer layer to complete transfer bonding.

Method of forming through-wafer interconnects for vertical wafer level packaging

This invention describes a method of stacking, bonding, and electrically interconnecting a plurality of thin integrated circuit wafers to form an interconnected stack of integrated circuit layers. The first integrated circuit layer is formed by conventional processing on a silicon wafer to the stage where bond pads are patterned on a wiring layer interconnecting the subjacent semiconductive devices. The remaining integrated circuit layers are formed by first processing a standard wafer to form integrated circuit devices and wiring levels up to but not including bond pads. Each of these wafers is mounted onto a handler wafer by its upper face with a sacrificial bonding agent. The wafer is thinned, permanently fastened to the top surface of the first base wafer by a non-conductive adhesive applied to the thinned under face, and dismounted from the handler. Vertical openings are etched through the thinned layer to the bond pads on the subjacent wafer. Robust conductive pass-through plugs with integrated upper bond pads are formed in the openings. Additional thinned integrated circuit layers may be prepared, thinned, cemented onto the stack. Wiring interconnections can be made between any two or more layers. The process is unique in that it can be used to further stack and interconnect any number of thinned wafer layers to form a three dimensional integrated circuits, including MEMS devices. This approach provides a low temperature wafer bonding method using an adhesive which results in process simplicity and cost effectiveness by eliminating an additional masking and patterning process for under bump metal thereby enabling standard wafers to be integrated into a 3D stack with existing wire bonded wafers.

Method of stacking thin substrates by transfer bonding

Fully salicided (FUSA) MOSFET structure

A wafer is provided having through-holes therein to form a through-hole via wafer. A substrate of a sacrificial wafer is provided. The substrate is coated with a polymer having low adhesion to metals. A conductive layer is deposited on the polymer. A photoresist layer is coated on the conductive layer. The through-hole via wafer is bonded to the sacrificial wafer wherein the photoresist layer provides the bonding. The photoresist exposed in the through-holes is developed away to expose the conductive layer. The through-holes are filled with a conductive material by electroplating the conductive layer. The photoresist is stripped in an ultrasonic bath wherein the photoresist separates from the through-hole wafer and wherein the filled through-holes separate from the polymer at an interface between the polymer and the conductive layer to complete separation of the through-hole via wafer from the sacrificial wafer.

Method of fabricating a micro-mirror switching device in single crystal silicon are described. The device is fabricated as three main elements: silicon mirror plate with metal-mirror, secondary actuator, and hinge/spring mechanism to integrate the mirror plate with the actuator. p-n junction is first formed on p-type silicon. Trenches are then etched in n-silicon to define the device element boundaries and filled with silicon dioxide. Three layers of sacrificial oxide and two structural poly-silicon layers are deposited and patterned to form device elements. Novel release processes, consisting of backside electrochemical etching in potassium-hydroxide, reactive ion etching to expose oxide-filled trenches from the bottom, and hydrofluoric acid etching of sacrificial oxide layers and oxide in silicon trenches, form the silicon blocks; those that are not attached to structural poly-silicon are sacrificed and those that are attached are left in place to hold together the switching device elements.

Method of fabricating micro-mirror switching device

A method for forming wafers having through-wafer vias for wafer-level packaging of devices, the method comprising the steps of depositing metal on one of two wafers; bonding the two wafers using the metal deposited on the one of the two wafers; forming a through-wafer via in one of the two wafers; filling the through-wafer via with a conductive material; and forming a cavity in the one of the two wafers having the through-wafer via wherein the cavity is superposable over a device.

Wafer-level package for micro-electro-mechanical systems

Inter-connectors are typically used for interconnecting electronic components. Interconnections between electronic components are generally classified into at least two broad categories of &ldquo;relatively permanent&rdquo; and &ldquo;readily demountable&rdquo;. A &ldquo;readily demountable&rdquo; connector includes a spring-like contact structure of one electronic component for connecting to a terminal of another electronic component. The spring-like contact structure, also known as an inter-connector, generally requires a certain amount of contact force to effect reliable pressure contact to a terminal of an electronic component. Therefore, the shape and metallurgy of the inter-connector are important factors in determining the effectiveness of the inter-connector for making pressure connection to a terminal of the electronic component. Conventional methods of making such an inter-connector use lithographic and planarisation methods to &ldquo;make&rdquo; the inter-connectors in segments. This results in the inter-connector segments having joints therebetween. Metallurgically, the joint stress due to joining a pair of inter-connector segments and stress concentration at the joints due forces applied to the inter-connector can lead to the mechanical failure of the inter-connector in Mathieu. An embodiment of the invention uses lithographic techniques and heat treatment methods for forming a structure channel defining the shape and dimension of an inter-connector. The structure channel is then used to &ldquo;mold&rdquo; a reproduction of the inter-connector having a single continuous physical segment.

Wafer-level inter-connector formation method

Method and apparatus for fluid-based cooling of heat-generating devices are disclosed. A heat-generating device is mounted on a carrier. The heat-generating device is spatially displaced from the surface of the carrier, thereby forming a channel. The heat-generating device and the carrier are enclosed in an enclosure having an inlet and an outlet. A substantially electrically non-conductive cooling fluid for introduction into the enclosure and into the channel and expulsion from the enclosure and for extracting heat from and thereby cooling the heat-generating device and the carrier.

Apparatus and method for fluid-based cooling of heat-generating devices

Growing community of inventors

Singapore, Singapore

Ranganathan Nagarajan