Applied Materials, Inc.

Ranga Rao Arnepalli

Robert Jan Visser

Prerna Sonthalia Goradia

Nilesh Chimanrao Bagul

Abhijit Basu Mallick

Fred Conrad Redeker

Sivapackia Ganapathiappan

Nag B Patibandla

Rajeev Bajaj

Pramit Manna

Arvind Sundarrajan

Daniel Redfield

Guan Huei See

Yan Zhao

Ashavani Kumar

Boyi Fu

Ashwin Chockalingam

Prayudi Lianto

Mario Dagio Cornejo

Darshan Thakare

Amritanshu Sinha

Nitin K Ingle

Mikhail Korolik

Pravin K Narwankar

Lance A Scudder

Kaushal Kishore Singh

Yuriy Melnik

Omkaram Nalamasu

Bhaskar Kumar

Sukti Chatterjee

Colin Costano Neikirk

Jie Zeng

Tapash Chakraborty

Gaurav Saraf

Suresh Chand Seth

Srikant Rao

Claire J Carmalt

Sanjayan Sathasivam

Christopher Stuart Blackman

Jayeeta Biswas

Saurabh Lodha

Embodiments described herein relate to integrated abrasive (IA) polishing pads, and methods of manufacturing IA polishing pads using, at least in part, surface functionalized abrasive particles in an additive manufacturing process, such as a 3D inkjet printing process. In one embodiment, a method of forming a polishing article includes dispensing a first plurality of droplets of a first precursor, curing the first plurality of droplets to form a first layer comprising a portion of a sub-polishing element, dispensing a second plurality of droplets of the first precursor and a second precursor onto the first layer, and curing the second plurality of droplets to form a second layer comprising portions of the sub-polishing element and portions of a plurality of polishing elements. Here, the second precursor includes functionalized abrasive particles having a polymerizable group chemically bonded to surfaces thereof.

Integrated abrasive polishing pads and manufacturing methods

Methods of removing native oxide layers and depositing dielectric layers having a controlled number of active sites on MEMS devices for biological applications are disclosed. In one aspect, a method includes removing a native oxide layer from a surface of the substrate by exposing the substrate to one or more ligands in vapor phase to volatize the native oxide layer and then thermally desorbing or otherwise etching the volatized native oxide layer. In another aspect, a method includes depositing a dielectric layer selected to provide a controlled number of active sites on the surface of the substrate. In yet another aspect, a method includes both removing a native oxide layer from a surface of the substrate by exposing the substrate to one or more ligands and depositing a dielectric layer selected to provide a controlled number of active sites on the surface of the substrate.

Method, materials and process for native oxide removal and regrowth of dielectric oxides for better biosensor performance

A fan-out process using chemical mechanical planarization (CMP) reduces the step-height between a semiconductor die and the surrounding overmolding of a reconstituted wafer. The reconstituted wafer is formed by overmolding a back side of at least one die that is placed with an active side facing down. The reconstituted wafer is then oriented to expose the die and the active side. A polymer layer is then formed over the reconstituted wafer. A CMP process then removes a portion of the polymer layer until a certain thickness above the die surface is obtained, reducing the step-height between the polymer layer on top of the die surface and the polymer layer on the adjacent mold compound surface. The CMP process can also be performed after a subsequent redistribution layer is formed on the reconstituted wafer.

Methods and apparatus for semiconductor package processing

Single source precursors, methods to synthesize single source precursors and methods to deposit nanowire based thin films using single source precursors for high efficiency thermoelectric devices are provided herein. In some embodiments, a method of forming a single source precursor includes mixing a first compound with one of SbX, SbX, Sb(SO)or with one of BiX, Bi(NO), Bi(OTf), Bi(PO), Bi(OAc), wherein the first compound is one of a lithium selenolate, a lithium tellurolate, a monoselenide, or a monotelluride.

Methods to synthesize single source precursors and methods to deposit nanowire based thin films for high efficiency thermoelectric devices

A slurry for chemical mechanical planarization includes water, 1-3 wt. % of abrasive particles having an average diameter of at least 10 nm and less than 100 nm and an outer surface of ceria, and &#xbd;-3 wt. % of at least one amine.

Slurry for polishing of integrated circuit packaging

Systems and methods for forming films on the surface of a substrate are described. The systems possess aerosol generators which form droplets from a liquid solution made from a solvent and a deposition precursor. A carrier gas may be flowed through the liquid solution and push the droplets toward a substrate placed in a substrate processing region. The droplets pass into the substrate processing region and chemically react with the substrate to form films. The temperature of the substrate may be maintained below the boiling temperature of the solvent during film formation. The solvent imparts a flowability to the forming film and enable the depositing film to flow along the surface of a patterned substrate during formation prior to solidifying. The flowable film results in bottom-up gapfill inside narrow high-aspect ratio gaps in the patterned substrate.

Flowable gapfill using solvents

Systems and methods for processing films on the surface of a substrate are described. The systems possess aerosol generators which form droplets from a condensed matter (liquid or solid) of one or more precursors. A carrier gas is flowed through the condensed matter and push the droplets toward a substrate placed in a substrate processing region. An inline pump connected with the aerosol generator can also be used to push the droplets towards the substrate. A direct current (DC) electric field is applied between two conducting plates configured to pass the droplets in-between. The size of the droplets is desirably reduced by application of the DC electric field. After passing through the DC electric field, the droplets pass into the substrate processing region and chemically react with the substrate to deposit or etch films.

Low vapor pressure aerosol-assisted CVD

Systems and methods of etching a semiconductor substrate may include flowing an oxygen-containing precursor into a substrate processing region of a semiconductor processing chamber. The substrate processing region may house the semiconductor substrate, and the semiconductor substrate may include an exposed metal-containing material. The methods may include flowing a nitrogen-containing precursor into the substrate processing region. The methods may further include removing an amount of the metal-containing material.

Self-limiting atomic thermal etching systems and methods

A method of processing includes: providing a substrate having a contaminant material disposed on the copper surface to a substrate support within a hot wire chemical vapor deposition (HWCVD) chamber; providing hydrogen (H) gas to the HWCVD chamber; heating one or more filaments disposed in the HWCVD chamber to a temperature sufficient to dissociate the hydrogen (H) gas; exposing the substrate to the dissociated hydrogen (H) gas to remove at least some of the contaminant material from the copper surface; cooling the one or more filaments to room temperature; exposing the substrate in the HWCVD chamber to one or more chemical precursors to deposit a self-assembled monolayer atop the copper surface; and depositing a second layer atop the substrate.

Methods and apparatus for in-situ cleaning of copper surfaces and deposition and removal of self-assembled monolayers

Embodiments of the invention provide a method of forming a doped gallium arsenide based (GaAs) layer from a solution based precursor. The doped gallium arsenide based (GaAs) layer formed from the solution based precursor may assist solar cell devices to improve light absorption and conversion efficiency. In one embodiment, a method of forming a solar cell device includes forming a first layer with a first type of dopants doped therein over a surface of a substrate, forming a GaAs based layer on the first layer, and forming a second layer with a second type of dopants doped therein on the GaAs based layer.

High efficiency thin film transistor device with gallium arsenide layer

Growing community of inventors

Krishna, India

Ranga Rao Arnepalli