S3 Incorporated, Inc.

S3 Graphics Co., Ltd.

Randy X Zhao

Dong-Ying Kuo

Roger Niu

Sreenivas R Kottapalli

Eric S Young

Anoop Khurana

Lin Chen

Chih-Hong Fu

Zhou Hong

Steve Fong

Poornachandra Rao

Jeremy Alves

Chien-Te Ho

A system and method for increasing effective bus bandwidth in communicating with a graphics device. Graphics commands and associated parameters are written into a contiguous region of system memory and transmitted in a weakly ordered fashion over a bus to a graphics device. The graphics device reorders the incoming data into the same order as which the data was written into the contiguous region of system memory, thereby allowing the use of order dependent encoded commands with the weakly ordered bus interface.

Command reordering for out of order bus transfer

A command parser,is coupled to an incoming data stream to insert an end of state token at the end of a group of state data,and an end of primitive token at the end of a group of primitive data,to create a parsed data stream. The parsed state data stream is transmitted to a state controller,which loads state data,into shadow stages,The state controller,validates a shadow stage,upon receiving an end of state group token. The parsed primitive data,are also transmitted to primitive controllers,The primitive controllers,prevent primitive data from being transmitted into a processing element,responsive to receiving an end of primitive_B token. Upon receiving an end of primitive_E token, the primitive controller,ascertains whether the first shadow stage,has been validated. If it has, the primitive controller,loads the state data,into the working stage,and allows the primitive data,to be transmitted to the processing element,where it is processed in accordance with the state data,in the working stage,In an alternate embodiment, a dirty bit,is used to indicate that the state data,received by the state controller,is identical to previously received state data,The primitive controller,ascertains whether the dirty bit,of the first shadow stage,associated with its processing element,is marked. If the dirty bit,is unmarked, the primitive controller,allows the primitive data,to be processed by the processing element,without delay in accordance with the existing state information in the working registers.

State parser for a multi-stage graphics pipeline

A dither unit preferably comprises an offset generator, an adjusted coordinate generator and a dither matrix. The offset generator is coupled to receive information about the relative position of the sub-sample being dithered, and in response generates offset values. The output of the offset generator along with the pixel coordinates are provided to the adjusted coordinate generator which generates adjusted coordinate values used by the dither matrix. The adjusted coordinate values along with a color value are received by the dither matrix, which in response, generates a dithered value for the sub-sample that can be stored back in the over sampling buffer for additional computation.

System and method for performing dithering with a graphics unit having

The present invention provides an alpha blending unit that is able to perform alpha blending on sub-samples of a pixel in an efficient manner. The alpha blending unit preferably comprises a plurality of registers for storing a source color, a blending value, and a plurality of destination sub-sample values, multipliers, adders, an accumulator and a divider. The alpha blending unit advantageously sums the destination sub-sample values and then divides them by the number of sub-samples to generate a combined destination color value. This combined destination color value along with the source color and a blending value are then provided to the multipliers, and adders to generate a new destination color value for the pixel.

System and method for performing blending using an over sampling buffer

A caching system for increasing the operation concurrency between a cache module and a memory module by comparing received memory block identifiers, which correspond to texels needed for pixel composition, with memory block identifiers corresponding to texels locally stored within the cache module. If the received memory block identifiers match the memory block identifiers corresponding to locally cached texels, the system transmits these texels to a texture filter unit for pixel composition. If the received memory block identifiers do not match memory block identifiers corresponding to the locally cached texels, the system retrieves these texels from the memory module as fast as possible and then updates the cache module with the new texels. A plurality of first in, first out buffers are used to assist a controller module with synchronizing the transmission of the texels from the cache module and the overwriting of the texels received from the memory module into the cache module. Once locally cached, these texels also are transmitted to the texture filter unit for pixel composition.

Non-stalled requesting texture cache

A system and method for traversing and rendering a graphic primitive represented in screen space, employing block- and band-oriented traversal algorithms in texture mapping. Improved performance is achieved through burst-mode texture access and texture caching in connection with a texture map subdivided into squares. Block- and band-oriented traversal facilitates minimization of page breaks and texture cache swap-out. Improved determinism is facilitated by obviating the need for pixel sorting algorithms. Improved re-use of retrieved data segments in burst-mode access is facilitated.

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Fremont, CA, United States of America

Randy X Zhao