Microchip Technology Inc.

Other

Randy L Yach

Rodney J Drake

Joseph W Triece

Richard L Hull

Igor Wojewoda

Sumit K Mitra

Darrel Johansen

Kent D Hewitt

Greg Dix

Jennifer Yuan Chiao

Edward Brian Boles

Philippe Deval

Ward Brown

Gregory Dix

Donald S Gerber

Thomas Youbok Lee

Patrick Besseux

Gianpaolo Spadini

Rohan Braithwaite

Tommy Stevens

Steve Allen

Roger D St Amand

David M Susak

Vincent Quiquempoix

James B Nolan

Joseph Alan Thomsen

Brian E Boles

Sam E Alexander

Ray L Allen

Joshua M Conner

Steven Schlanger

James H Grosbach

Steve Vernier

Alan Lamphier

Francesco Mazzilli

Gregg Dix

James R Bartling

Arthur B Eck

Rohan S Braithwaite

Ward R Brown

James Grosbach

Rodney Jay Drake

Darrel Ray Johansen

Johansen Darrel

A capacitor structure may include a lower conducting layer (e.g., poly 1 layer) and an upper conducting layer (e.g., overlying poly 2 layer), which define an anode and cathode, and a dielectric layer (e.g., an ONO layer stack) located between the upper conducting layer and the lower conducting layer, wherein a portion of the dielectric layer (e.g., at least the nitride layer of the ONO layer stack) extends beyond a lateral edge of the upper conducting layer. A method forming such capacitor structure may utilize a spacer adjacent the lateral edge of the upper conducting layer and over the first portion of the dielectric layer, performing an etch to remove a first portion of the dielectric layer but protect a second portion located below the spacer and extending laterally beyond an edge of the upper conducting layer.

Capacitor structure with an extended dielectric layer and method of forming a capacitor structure

The teachings of the present disclosure may be applied to the manufacture and design of capacitors. In some embodiments of these teachings, a capacitor may be formed on a heavily doped substrate. For example, a method for manufacturing a capacitor may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate.

Capacitor formed on heavily doped substrate

The present disclosure relates to semiconductor manufacturing and the teachings of the present disclosure may be embodied in a semiconductor chip with an interconnect monitor. Some embodiments may include arrays of diodes on the semiconductor chip; each diode with a stack of vertical interconnects and metal contacts, the stack and the diode connected in series and control mechanisms for addressing the diodes. The control mechanisms may include first inverters for applying either a high or a low voltage to columns of the diode stacks, connected at one end of each diode stack. Each first inverter may include reverse logic receiving a reverse logic signal and configured to invert a logic signal fed to the device for applying a relatively high or low voltage and second inverters for applying either a high or a low voltage to rows of the diode stack in the one of the plurality of arrays, connected at a second end of said diode stack, wherein each second inverter comprises reverse logic receiving an inverted reverse logic signal and configured to invert a logic signal fed to the device for applying a relatively high or low voltage.

Interconnect monitor utilizing both open and short detection

At least one high voltage rated isolation capacitor is formed on a face of a primary integrated circuit die. The isolation capacitor AC couples the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitor DC isolates the primary integrated circuit from the second integrated circuit die.

Method and apparatus for constructing an isolation capacitor in an integrated circuit

A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET) comprises a substrate of a first conductivity type forming a drain region; an epitaxial layer of the first conductivity type on said substrate; first and second base regions of the second conductivity type within said epitaxial layer, spaced apart by a predefined distance; first and second source regions of a first conductivity type arranged in said first and second base regions, respectively, wherein said first and second base region is operable to form first and second lateral channels between said source region and said epitaxial layer; a gate structure insulated from said epitaxial layer by an insulation layer and arranged above the region between the first and second base regions and wherein the gate structure comprises first and second gate regions, each gate region only covering the first and second channel, respectively within said first and second base region.

Vertical DMOS-field effect transistor

High voltage rated isolation capacitors are formed on a face of a primary integrated circuit die. The isolation capacitors AC couple the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitors DC isolate the primary integrated circuit from the second integrated circuit die. Isolated power transfer from the first voltage domain to the second voltage domain is provided through the high voltage rated isolation capacitors with an AC oscillator or PWM generator. The AC oscillator voltage amplitude may be increased for an increase in power through the high voltage rated isolation capacitors, and a larger value capacitor in the second voltage domain may provide for peak current demand from circuits in the second voltage domain.

Integrated high voltage isolation using low value capacitors

A semiconductor chip for process monitoring of semiconductor fabrication, has a plurality of arrays with a plurality of diodes, each diode being formed in the chip, each diode being associated with a stack with at least one horizontal interconnect, the stack and the diode connected in series to form a diode stack combination, wherein the horizontal interconnect has a salicided polysilicon interconnect comprising complementary doped polysilicon sections to form a reverse biased diode.

Method and apparatus for monitoring semiconductor fabrication

A constant current output sink or source eliminates a current limiting series resistor for a light emitting diode (LED) and maintains a constant light intensity from the LED for all operating and manufacturing variables of a digital device since the current through the LED is maintained at a constant value. The constant current output sink or source may be programmable for selection of a constant current value from a plurality of constant current values available.

Constant current output sink or source

A remote keyless entry (RKE) transponder has a programmable selective wake-up filter for determining whether the RKE transponder should wake-up to process a received signal. The wake-up filter correlates the timing of an input signal's carrier amplitude on and off time periods to a predefined programmable time period profile for a desired signal which has a certain carrier on time (time period on) and a certain carrier off time (time period off) arranged into a coded 'header.' When a received signal matches the predefined time period profile, then the RKE transponder will wake-up to process the incoming signal data. The predefined time period profile may be programmable and may be stored in a header configuration register. Each RKE transponder has unique predefined time period on and time period off profiles.

Programmable selective wake-up for radio frequency transponder

A method for monitoring a semiconductor fabrication process creates a wafer of semiconductor chips. Each chip has a one or more diodes. Each diode is addressable as part of an array, corresponds to a physical location of the chip, and is connected in series to a stack. The stack is composed of one ore more vertical interconnects and metal contacts. The diode and associated stack of vertical interconnects is addressed, and the current through each of the stacks of vertical interconnects in an array is measured.

Method and apparatus for monitoring via's in a semiconductor fab

Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capacitive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

Adaptive electrostatic discharge (ESD) protection of device interface for local interconnect network (LIN) bus and the like

A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performances and decreasing program memory usage.

Microcontroller instruction set

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Phoenix, AZ, United States of America

Randy L Yach