Intel Corporation

Randy L Steck

Glenn J Hinton

Konrad K Lai

James A Valerio

Gurbir Singh

Frank S Smith

Michael T Imel

Phillip G Lee

Eileen Riggs

Robert B Chaput

Glenford J Myers

A method and apparatus for providing a non-blocking cache that uses substantially less die area than a prior art non-blocking cache. In the present invention, pending count and ignore fill fields are added to each line of the cache. These fields are used in conjunction with a valid field (that indicates whether or not the line contains valid data) to keep track of the status of pending load operations that have resulted in cache misses. The pending field keeps a count of the number of outstanding load misses for the line. If a store occurs for an address of a line, the ignore fill field is set to indicate that any fills that are pending for the line are to be ignored because the pending fills will be supplying stale data to the line.

Method and apparatus for a line based non-blocking data cache

An interface protocol between a microprocessor register file (6) and a plurality of first functional units capable of independently executing first microinstructions that take a plurality of clock cycles to complete execution. A plurality of second functional units capable of independently executing second microinstructions that take a single clock cycle to complete execution. The first and second microinstructions are issued by an instruction decoder. A microintruction bus (112) is connected to the instruction decoder, the register file, and to each of the first and second functional units. A REG interface and a destination bus (110) are also connected to the register file (6). A Scbok line (102) is connected between the instruction unit, the register file and to each one of the first and second functional units. The instruction decoder includes means for asserting the Scbok line to signal that a current microinstruction on the microintruction bus (112) is valid. Means in the register file disassert the Scbok signal upon the condition that any one register in the register file needed by the instruction on the microinstruction bus is busy. An EU write line (102) connected from one of the single cycle functional units to the multiple cycle functional units is asserted by one of the single cycle functional units upon the condition that the single cycle functional unit requests access to the destination bus. The multiple cycle functional units and single cycle functional units are connected to the REG interface and to the destination bus. Arbitration means (3) in each of the multiple cycle functional units respond to the EU write line and to the Scbok line to prevent access to the destination bus upon the condition that the EU write line and the Scbo k line are asserted.

Interface between a register file which arbitrates between a number of

A data processing system which includes a microprocessor fabricated on an integrated circuit chip, a main memory external to the integrated circuit chip, and a backside cache external to the integrated circuit chip. The backside cache includes a directory RAM for storing cache address tag and encoded cache state bits. A first bus connects the microprocessor to the cache, the first bus including backside bus cache directory tags signals comprised of address bits used for a cache hit comparison in the directory RAM and backside bus cache directory state bits for determining a state encoding of a set in the directory RAM. A second bus connects the microprocessor to the main memory. The directory includes means for comparing the cache directory tags on the first bus with the tags stored in the directory and for asserting a Bmiss signal upon the condition that the directory tag stored in the backside bus cache directory do not match the backside bus cache directory tags signals. The microprocessor responds to the Bmiss signal by issuing the access onto the second bus in the event of a cache miss.

Microprocessor simultaneously issues an access to an external cache over

Apparatus for performing mixed precision calculations in the floating point unit of a microprocessor from a single instruction opcode. 80-bit floating-point registers (44) may be specified as the source or destination address of a floating-point instruction. When the address range of the destination indicates (26) that a floating point register is addressed, the result of that operation is not rounded to the precision specified by the instruction, but is rounded (58) to extended 80-bit precision and loaded into the floating point register (FP-44). When the address range of the source indicates (26) that an FP register is addressed, the data is loaded from the FP register in extended precision, regardless of the precision specified by the instruction. In this way, real and long-real operations can be made to use extended precision numbers without explicitly specifying that in the opcode.

Mixed-precision floating point operations from a single instruction

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Hillsboro, OR, United States of America

Randy L Steck