Agilent Technologies, Inc.

Hewlett-packard Company

Other

Verigy Ipco

Randy L Bailey

Alan S Krech, Jr

Romi Mayder

John M Freeseman

Andrew Tse

Byron Alan Alcorn

Edmundo De La Puente

Robert Keith Barnes

Lance D Bailey

Brian Daniel Beck

Howard D Stroyan

Susan E Bailey

Douglas C Beethe

David R Herdrich

Noriyuki Sugihara

Brad D Reak

Todd Sholl

Nasser Ali Jafari

James P Armentrout

A raised gutter cover that is live loaded and acts as a compressions spring when mounted on a gutter hung with high-hangers and securely attaches the gutter cover to the gutter and the building allowing water shed from the pitched roof to separate from any debris and strain through the gutter.

Raised gutter cover

A clipping apparatus is described herein. The clipping apparatus may include a u-shaped clasp and a tab. The clasp may include an open end and a closed end, a first side and a second side, and a tongue. The tab may be coupled to, and extend from, the closed end of the clasp. The first side may include a wall extending from the closed end to the open end. The second side may include two prongs extending from the closed end to the open end. The tongue may be rotatably connected to the two prongs between the two prongs. The tab may include a first opening and a second opening. The first opening may be disposed in the tab adjacent to the closed end of the clasp. The second opening may be disposed in the tab at a distal end to the tab from the clasp.

Clip, hanger and method of using the same

A parallel calibration system for an electronic circuit tester comprises test and measurement electronics, a test fixture coupled to the test and measurement electronics, the test fixture comprising clock reference circuitry and clock distribution circuitry, a device under test interface, and a plurality of calibration boards coupled to the device under test interface, wherein the plurality of calibration boards and the clock distribution circuitry simultaneously test the signal paths of a plurality of test channels.

Parallel calibration system for a test device

A trigger signal for a memory tester uses a (breakpoint) trigger qualified according to what part of the test program is being executed. The qualified breakpoint trigger can be delayed before becoming a system trigger signal that can be used to trigger a 'scope mode and to force an error flag to a selected value so as to compel a particular path with the test program. To provide stable waveforms for the sweeping of the voltage thresholds and sample timing offset the memory tester records the addresses for a target sequence of transmit vectors issued during an initial pass through the test program subsequent to the occurrence of the trigger. These addresses are exchanged for the instructions themselves, which are then altered to remove branching, and stored in a reserved portion of the memory they came from. Once the altered target sequence is stored the desired information is produced by restarting the entire test program and letting it run exactly as before down to the trigger. Now when the trigger occurs further transmit vectors are issued from the memorized target sequence, rather than from the live algorithm, and a combination of voltage thresholds and the sample timing offset are switched into place. After the target sequence the test program is re-started with normal thresholds and sample timing offsets. There is eventually another trigger, whereupon the memorized target sequence is again substituted while the next combination in the step along the acquisition sweep is instituted. This process is continued until the entire acquisition sweep has been performed. An inspection of the stored data allows creation of the waveforms.

Algorithmically programmable memory tester with breakpoint trigger, error jamming and 'scope mode that memorizes target sequences

A memory tester supports testing of multiple DUT's of the same type at a test site. The tester can be instructed to replicate the segments of the test vectors needed to test one DUT on the channels for the other DUT's. This produces patterns of transmit and receive vectors that are n-many DUT's wide. Conditional branching within the test program in response to conditions in the receive vectors (DUT failure) is supported by recognizing several types of error indications and an ability to selectively disable the testing of one or more DUT's while continuing to test the one or more that are not disabled. Also included are ways to remove or limit stimulus to particular DUT's, and ways to make all comparisons for a particular DUT appear to be &ldquo;good.&rdquo;

Memory tester tests multiple DUT's per test site

Systems and methods for calibrating the timing of electronic circuit testers and verifying the timing calibration of electronic circuit testers are described. In some embodiments, a calibration reference signal is transmitted from the test head directly through the load board interface, rather than through external instruments, so that timing errors associated with external wires and cables may be avoided. The timing calibration and timing calibration verification functionality is provided on a single calibration board, thereby reducing the calibration set-up time relative to conventional robot-based calibrators. In addition, a high pin count electronic circuit testers may be calibrated by a calibration board that is configured to calibrate one subset of the test channels at a time. In some embodiments, test channels are connected directly to calibration board comparators to avoid the accumulated signal degradation and the signal path route errors that may result from transmitting tester channel signals through a mechanical relay selection matrix.

Timing calibration and timing calibration verification of electronic circuit testers

A precision delay system allowing clock edges to be delayed with new delay values every clock period T. The internal delay elements are reprogrammed every clock cycle with reprogramming transients suppressed by clock independent blanking circuitry. The system allows the use of delay elements with a maximum delay of one-half (T/2) the clock period to continuously span a full clock cycle T delay range with full cycle-by-cycle reprogramming.

Precision, high speed delay system for providing delayed clock edges with new delay values every clock period

An improved method of incorporating a high performance graphics device into a base graphics subsystem of a processor includes two pairs of interface chips. One pair of interface chips is used to transfer pixel data between a base graphics system and the high performance graphics device, while the second pair of interface chips is used to transfer commands between the graphics device and the base graphics system. One of the pair of interface chips that is used to transfer pixel data is coupled to a bus within the base graphics subsystem while the second one of the pair is coupled to the graphics device. With such an arrangement, a high speed interface allows for pixel data to be fed directly to the frame buffer of the graphics subsystem, enabling the windows that are rendered by two different graphics systems to share a frame buffer memory.

Multiple graphics pipeline integration with a windowing system through

An iconic programming system that provides a sequencer icon to allow a series of operations to be performed, along with the conditions under which the operations are performed. Each operation performed, called a transaction, can be enabled or disabled, or can be enabled by a function within the process. The results of each transaction can be compared to tolerance limits and alternate subsequent transactions processed based upon whether the transaction results fell within the tolerance limits. The output of each transaction can be logged into a buffer to keep the results for later analysis.

Growing community of inventors

Fort Collins, CO, United States of America

Randy L Bailey