Intel Corporation

Randy L Allmon

Ram K Krishnamurthy

Sanu K Mathew

Mark A Anders

Himanshu Kaul

William C Hasenplaugh

David Lin

Balkaran Gill

Norbert Roland Seifert

Mondira D Pant

Vinod Ambrose

Jonathan Enoch

Jeffrey D Pickholtz

Paul Gronowski

Shah M Jahinuzzaman

Manjunath Bhat

An apparatus is described having a latch circuit. The latch circuit includes redundant data inputs, redundant data outputs, redundant clock inputs and circuitry to self-correct a soft-error.

Latch with redundancy and circuitry to protect against a soft error

Embodiments of the present invention may provide methods and circuits for energy efficient floating point multiply and/or add operations. A variable precision floating point circuit may determine the certainty of the result of a multiply-add floating point calculation in parallel with the floating-point calculation. The variable precision floating point circuit may use the certainty of the inputs in combination with information from the computation, such as, binary digits that cancel, normalization shifts, and rounding, to perform a calculation of the certainty of the result. A floating point multiplication circuit may determine whether a lowest portion of a multiplication result could affect the final result and may induce a replay of the multiplication operation when it is determined that the result could affect the final result.

Variable precision floating point multiply-add circuit

In some embodiments, complementary charge-collecting diffusions (transistor diffusions, e.g., drain or source areas) are disposed close to each other. In some embodiments, dummy ('off') transistors are incorporated to bring complementary diffusions (diffusions of the same charge type and having complementary digital logic levels) closer to each other than otherwise might be possible and thus, to enhance common-mode charge collection for the complementary diffusion areas.

Soft error reduction circuit and method

A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an evaluation phase defined by the clock signal. A static output is based on the latched value. One of the logic gates is tri-stateable to establish a value at the static output during a scan mode. A circuit for converting received static logic signals into domino logic signals includes a latch responsive to a clock signal to latch the value of a data signal at a predefined clock transition. A conversion circuit produces a domino logic output signal in response to the clock signal and the latched value of the data signal. A latch component is tri-stateable to establish a value at the output.

Scan friendly domino exit and domino entry sequential circuits

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North Grafton, MA, United States of America

Randy L Allmon