Xilinx, Inc.

Western Digital Technologies, Inc.

Hgst Netherlands, B.v.

Randy J Simmons

David Mark

Cherngye Hwang

Andrew W Lai

Teymour M Mansour

Lee Ni Chung

Eduardo Torres

Andy T Nguyen

Sridhar Krishnamurthy

Jay T Young

Min Luo

Shankar Lakkapragada

Jeffrey V Lindholm

Tuyet Ngoc Simmons

Vincent L Tong

Arnold Y Louie

Felino E Pagaduan

William R Troxel

Jian Jun Shi

Tony Le

Arnold Abrera Cruz

Yung-Cheng Chen

Dahshi Shen

Huy-Quang Le

Kazi S Afzal

Srinivasa R Parthasarathy

Embodiments herein describe techniques for binning integrated circuits (ICs) using an adaptive binning system that can re-bin the ICs in response to receiving a new or updated test specification. Unlike static binning systems, in one embodiment, the binning system receives measured test data from a testing system. Put differently, instead of a testing apparatus simply indicating whether an IC does (or does not) satisfy the criteria in the test specification, the testing apparatus provides measured test data to the binning system. The binning apparatus can then store the received test data. As such, if a new test specification is received or generated, the binning system can use the already saved test data to re-bin the ICs using the criteria in the new test specification without having to re-test the ICs. In this manner, the binning system can re-categorize the ICs as customer needs or customer demand changes.

Flexible manufacturing flow enabled by adaptive binning system

Embodiments disclosed herein generally relate to a method for forming a HAMR head. The method includes depositing a drop-on-demand mask on a portion of a surface of a slider using a drop-on-demand tool. The surface of the slider includes at least a portion of an NFT. A first protective layer is deposited over a remaining portion of the surface of the slider and over the drop-on-demand mask. The drop-on-demand mask and a portion of the first protective layer disposed on the drop-on-demand mask are removed, exposing at least the portion of the NFT. A second protective layer is deposited on the first protective layer and at least the exposed portion of the NFT. By using the drop-on-demand tool to deposit the drop-on-demand mask, the alignment between the drop-on-demand mask and the portion of the NFT is less stringent, and the drop-on-demand mask can be easily removed using a wiping tool.

Method to coat NFT area with highly thermal conducting material in HAMR structure

Operation of an internal voltage supply level (Vgg) of an IC is characterized over operating temperature or at a selected temperature to determine a temperature-equivalent internal voltage level. The internal voltage supply of the IC is set to the temperature-equivalent level, and the IC is tested at room temperature to screen for low-temperature defects or high-temperature defects.

Internal voltage level shifting for screening cold or hot temperature defects using room temperature testing

Method and apparatus for testing input/output circuits of an integrated circuit are described. An integrated circuit includes input/output circuits having input/output pads. The input/output pads are capable of being coupled together to a tester channel. The input/output circuits each are configurable via configuration circuitry to be in either a first mode or a second mode responsive to a select circuit of the configuration circuitry coupled to receive a first input for the first mode and a second input for the second mode. The select circuit is controlled responsive to a control select signal common to all or a portion of the select circuits of each of the input/output circuits.

Testing of input/output devices of an integrated circuit

A method and apparatus for substantially eliminating noise induced errors caused by a premature start-up sequence between configuration of an integrated circuit (IC) and execution of functional test vectors. A noise elimination sequence is executed, whereby the configuration bitstream associated with the IC is scanned for the existence of a start-up sequence. If found, the start-up sequence is stripped from the configuration bitstream and the IC is then configured using the modified configuration bitstream. The input/output (I/O) pins of the IC remain in a deactivated state until a startup sequence is transmitted to the IC via a Joint Test Action Group (JTAG) port of the IC, which then allows IC testing to commence.

Method and apparatus for eliminating noise induced errors during test of a programmable logic device

A method and test configuration for performing a gross I/O functionality test at wafer sort is described. The method uses a current injector, such as a pullup or a pulldown on an I/O pad, to inject current at the I/O pad, and based on the resulting voltage, determines if the I/O characteristics of the IC meet the performance criteria set by a manufacturer. In some embodiments, the test configuration can comprise an output buffer, which can be a tristate buffer, and/or an input buffer for verifying the performance of those components. The method and test configuration allow such tests to be performed at wafer sort without a precision measurement unit and without direct access to the I/O pad to be tested.

Method for gross I/O functional test at wafer sort

Methods and systems for testing PLD interconnect lines, e.g., interconnect lines driven by a plurality of programmable buffers. Each programmable buffer has an associated memory element. The memory elements are configured to form a shift register, with one of the buffers and the interconnect line inserted between two of the memory elements. The signal path through the shift register is tested using a first test pattern. Partial reconfiguration is then used to change the insertion point of the interconnect line in the signal path by changing the configuration of the interconnect structure and using a second one of the buffers. A second test pattern is then used to test the second buffer. This sequence is repeated until each of the buffers has been tested. Because only small changes are required, the partial reconfiguration requires loading only small amounts of configuration data, significantly reducing test time compared to presently-known test methods.

Methods of testing interconnect lines in programmable logic devices using partial reconfiguration

Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a device model is provided to the user that prevents the use of these resources. Because the routing resources will never be used, they need not be tested by the PLD manufacturer, significantly reducing the test time. For example, each PLD within a PLD family is typically designed using a different number of similar tiles. Thus, smaller PLDs in the family include an unnecessarily large number of routing resources. These excessive routing resources can be disabled during implementation of a design. In another example, each tile along the edges of an array includes routing resources designed primarily to provide access to tiles that are not present. These redundant routing resources can be disabled during implementation of a design.

Methods of resource optimization in programmable logic devices to reduce test time

A test cell and method of operation are disclosed. The test cell may be cascaded with other test cells to form a test structure that spans across any number of slices and/or tiles in a programmable logic device. The test structure behaves like a register, and may be used to test direct interconnects and any number their fan-out lines simultaneously.

Test methodology for direct interconnect with multiple fan-outs

Method and apparatus for localizing faults within an integrated circuit is described. For example, a programmable logic device (PLD) is configured with a test pattern. A test stimulus is applied to the test pattern. State data responsive to the test pattern is obtained. The state data may be obtained from a readback datastream generated by the PLD. The expected state data may be generated by a second PLD that is known to contain no faults. The state data is compared with expected state data to produce difference information. The difference information is used, or more particularly is iteratively generated, to localize a fault or faults within a unit under test.

Method and apparatus for localizing faults within a programmable logic device

A method and test configuration for performing a gross input leakage test at wafer sort is described. The method uses a pullup and pulldown on an I/O pad to inject current at the I/O pad, and, based on the resulting voltage, determines if the leakage current is excessive. The method allows an input leakage test to be performed at wafer sort without a precision measurement unit and without direct access to the I/O pad to be tested.

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San Jose, CA, United States of America

Randy J Simmons