Intel Corporation

Marvell International Limited

Intle Corporation

Randy J Aksamit

Ming Lei Zhang

James W Tschanz

Greg F Taylor

Chris Wilkerson

Niti Goel

Silvio E Bou-Ghazale

Rany T Elsayed

Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.

Techniques for forming a compacted array of functional cells

Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache.

Apparatus and method to reduce memory power consumption by inverting data

Memory data inversion for reducing power consumption

Data inversion based approaches for reducing memory power consumption

In general, in one aspect, the disclosure describes an apparatus comprising a low leakage latch to store a state of a circuit during inactive periods. The state is transferred to the low leakage latch upon receipt of an inactive pulse. A buffer is used to receive the state from an output of the low leakage latch and to isolate the state. State restore circuitry is used to restore the state to the circuit when the circuit returns to an active mode. The state restore circuitry is used to receive the isolated state and to restore the state upon receipt of an active pulse.

Low leakage state retention circuit

A clocked level-sensitive scan design may have flip-flops designed to have data, scan-in, and output ports and to utilize two clock signals. Such a clocked level-sensitive scan flip-flop may be built utilizing two latches.

Two-latch clocked-LSSD flip-flop

In embodiments, a data-retention circuitry comprises data-retention inverters in a feedback loop, an isolation subcircuit to isolate the inverters from a pass-gate subcircuit in response to a sleep signal, and a supply-switching subcircuit to provide current to the data-retention inverters from a supplemental voltage supply through a well tap during a standby mode. The supply-switching subcircuit switches from a regular voltage supply to the supplemental voltage supply in response to the sleep signal.

System and method for data retention with reduced leakage current

Gate array architecture

Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes at least one base site, the at least one base site being three tracks wide and including four N-type transistors and four P-type transistors. Briefly, in accordance with another embodiment of the invention, a method of fabricating an integrated circuit chip includes: processing a semiconductor substrate to form a gate array architecture of transistors in the substrate. The gate array architecture includes at least one base site being three tracks wide and including four N-type transistors and four P-type transistors. Briefly, in accordance with still another embodiment of the invention, an article includes: a storage medium, the storage medium having instructions stored thereon, the instructions, when executed, resulting in the capability to design the layout of an integrated circuit chip for fabrication, the integrated circuit chip including a gate array architecture, the gate array architecture including at least one base site being three tracks wide and including four N-type transistors and four P-type transistors.

Growing community of inventors

Chandler, AZ, United States of America

Randy J Aksamit