International Business Machines Corporation

Ncr Corporation

American Telephone & Telegraph Co., At&t Bell Laboratories

At&t Information Systems Inc.

Randy D Pfeifer

Greg R Dhuse

Andrew D Baptist

Ilya Volvovski

Manish Motwani

Niall John McShane

Hanz Werner Herrig

David N Horn

Daniel V Peters

Wayne R Wilcox

Roger W Ratz

A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device detects a potentially adverse storage issue with a memory device of a storage unit (SU) of set(s) of storage unit(s) (SU(s)). The computing device also determines whether to transfer at least one EDSs (associated with the memory device) to another memory device for temporary storage therein. Based on a determination not to transfer, the computing device identifies at least one alternate storage location and facilitates transfer of the at least one EDSs for temporary storage therein. When the potentially adverse storage issue has subsided, the computing device facilitates transfer of the at least one EDSs back.

Finding alternate storage locations to support failing disk migration

There is disclosed a telephone instrument having controller and audio unit portions coupled together by a control bus and a user data bus having four audio states. The audio unit portion comprises a state machine that allows operating modes of the telephony instrument to be monitored and controlled. The state machine places the user data bus in a first predetermined state and the controller portion responds by placing the control bus in a selected state. The state machine detects the selected state and, in response thereto, places the user data bus in a second predetermined state. The second predetermined state indicates whether the first predetermined state was intended to be one of the four audio states or one of at least two mode control states. The user data bus and the control bus cooperate to provide a sequential output having at least six states, thereby allowing the operating modes to be monitored and controlled without modifying the bus drive circuitry.

State machine and method for monitoring and controlling operating modes

A software-implemented bridging routine is provided for a full duplex audio telephone system comprising units A, B and C. of which only unit A need have at least two lines and be full duplex. Unit A receives and speaker-reproduces an audio signal B+C that echoes with a time delay dt.sub.1 and is detected by unit A's microphone as a signal k.sub.b Bdt.sub.1 +k.sub.c Cdt.sub.1, where k.sub.b and k.sub.c are co-efficients. Unit A's host software determines time dt.sub.1 and generates a delay dt.sub.2 .apprxeq.dt.sub.1. Unit A's host processor sums its own microphone output with a signal generated by a non-destination unit that is delayed by time dt.sub.2. Thus, when communicating with unit B, unit A's software generates a host processor output signal A+k.sub.b Bdt.sub.1 +k.sub.c Cdt.sub.1 +Cdt.sub.2. The k.sub.b Bdt.sub.1 echo component is removed by unit A's AEC, which is coupled between units A and B. This causes unit B to receive the signal A+Cdt.sub.2 +k.sub.c Cdt.sub.1 from unit A. Since dt.sub.2 .apprxeq.dt.sub.1, user B hears voice A summed with a slightly delayed voice C (e.g., Cdt.sub.2) superimposed with an attenuated in-phase version of voice C (e.g., k.sub.c Cdt.sub.1). User B thus hears user A's voice and user C's voice conversing naturally in a full duplex manner. Similarly, B hears user A and user C conversing, and user C hears user A and user B conversing. In this fashion, full-duplex operation is achieved without using hardware bridge circuitry.

Software-based bridging system for full duplex audio telephone

An electronic circuit board electrically connected to other circuits of a data processing system by means of a bus, may be removed and re-inserted in the system without the necessity of disabling other circuits connected to the bus. A latch actuated switch provides a control signal in anticipation of circuit board removal. The control signal activates a finite state machine which seizes control of the bus after completion of any current bus communications and stops the generation of clock pulses normally required in bus communications. When contact is physically broken between the board and its corresponding connector, the finite state machine restores the bus clock pulses and relinquishes control of the bus. When a board is to be inserted in an open connector, contact between the board and the connector is sensed by the finite state machine which causes the bus to be seized and the bus clock pulses to be temporarily inhibited. When the board is fully inserted, the finite state machine restores the bus clock pulses and relinquishes control of the bus.

Method and apparatus for controlled removal and insertion of circuit

To lock use of shared information to itself in a multiprocessor system (100) having two independently and asynchronously operating processors (101, 111) whose main store units (102, 112) duplicate each other's contents, a processor must cause an atomic read-modify-write (RMW) operation to be executed on a semaphore in the duplicated main store units of both processors. To properly order execution of multiple such RMW operations, arbiters (106, 116) of system buses (105, 115) of the two processors communicate over an interarbiter channel (121). The arbiter of a source processor that wishes to perform an RMW operation notifies the other processor's arbiter over the interarbiter channel. Simultaneous attempts at notification by both arbiters are resolved in favor of one of them that is designated the master. The notifying arbiter prevents its processor from performing another RMW operation until the one RMW operation has completed thereon, but permits other operations to proceed normally. The notified arbiter prevents its processor from performing another RMW operation until the one RMW operation has been transferred via interprocessor links (107, 117) and bus (120) from the source processor to the notified arbiter's processor and has been performed thereon, but permits other operations to proceed normally. Thus multiple RMW operations are performed on both processors in the same order asynchronously and without impacting performance of other operations.

Method of and arrangement for ordering of multiprocessor operations in a

Growing community of inventors

Warrenville, IL, United States of America

Randy D Pfeifer