Sgs-thomson Microelectronics Limited

Intel Corporation

Altera Corporation

Randy C Steele

Bruce A Doyle

Richard P Vireday

Safoin A Raad

Duane H Chinnow, Jr

Joseph H Salmon

Jay J Sturges

Gregory B Hibdon

Mike Allen

K K Ramakrishnan

A field programmable gate array (FPGA) comprising a number of configurable function blocks, each separately configurable by the user of the FPGA as either high performance programmable logic or a block of SRAM is disclosed. In accordance with the present invention, each configurable function block includes a volatile logic array comprised of an array of 'AND' gates and an array of 'OR' gates with programmable connections. The programmable connections in the volatile logic array comprise SRAM cells. These SRAM cells are then capable of serving the user of the FPGA in two modes of operation. In a first mode of operation, logic mode, the SRAM cells provide for the programmable connections which direct the logic operations in the volatile logic array. In a second mode of operation, memory mode, the SRAM cells function as a block of SRAM which can then be written to, and read from, using standard SRAM access signals.

Field programmable gate array with high speed SRAM based configurable

A field programmable gate array (FPGA) includes a number of configurable function blocks, each separately configurable by the user of the FPGA as either high performance programmable logic or a block of SRAM. In accordance with the present invention, each configurable function block includes a volatile logic array comprised of an array of 'AND' gates and an array of 'OR' gates with programmable connections. The programmable connections in the volatile logic array comprise SRAM cells. These SRAM cells are then capable of serving the user of the FPGA in two modes of operation. In a first mode of operation, logic mode, the SRAM cells provide for the programmable connections which direct the logic operations in the volatile logic array. In a second mode of operation, memory mode, the SRAM cells function as a block of SRAM which can then be written to, and read from, using standard SRAM access signals.

A decoding circuit for two sequential addresses including a function gate which shares both P type input transistor devices between input terminals and uses predecoders to remove P type devices from a central portion of available die space, and N type transistor devices by utilizing a pass gate device to join output terminals for the two sequential addresses when an address is not selected.

High density decoder

A programmable logic device having a plurality of gates which can be programmed to implement a plurality of product terms for representing logic functions, wherein an input signal is processed according to the logic functions, and a resulting output signal is generated having a selectable output voltage level. A desired output voltage level is specified. A generator supplies the desired output voltage to an output buffer of the programmable logic device. This generator may operate independently from the generator used to supply power to the programmable logic device. The processed signal drives the output buffer, and the output signal from the output buffer corresponds to the desired output voltage.

Programmable logic having selectable output voltages

A zero power circuit includes an upper power supply voltage pad, battery pad, a power control circuit, and a suppression circuit. The power control circuit provides power to the zero power circuit by switching between the battery pad and the upper power supply voltage pad. The suppression circuit is connected in series between the power control circuit and the battery pad. The suppression circuit includes a resistor connected in series between the battery pad and the power control circuit, wherein current flowing through the transistor during a latch condition causes the voltage to drop across the resistor, suppressing the latchup condition to the battery pad. The suppression circuit also includes a transistor connected in parallel with the resistor, the transistor having a gate, wherein a first signal applied to the gate turns off the transistor and a second signal applied to the gate turns on the transistor, wherein the resistor is shorted when the transistor is turned on.

Zero power latchup suppression circuit

A circuit for testing the accuracy with which data is written from a first memory cell to a second memory cell including a shift register including master and slave portions, apparatus for placing data from the first memory cell into the master portion of the shift register and shifting the data into the slave portion of the shift register, apparatus for placing the data from the first memory cell into the second memory cell, apparatus for placing the data in the second memory cell back into the master portion of the shift register, and logic circuitry for testing the condition of the data in the master portion of the shift register against the condition of the data in the slave portion of the shift register to determine if the data has been correctly written into the second memory cell.

Error detection circuit for power up initialization of a memory array

A deterministic method and apparatus for defining the size and switch assignments of a switch matrix. The method operates on a switch matrix having a number of inputs (N) and a number of outputs (M). When constructing the switch matrix, there will be M columns in the matrix. The method determines a minimum number of rows (R) for the switch matrix. The resultant general purpose R.times.M switch matrix allows any combination of a subset of the N inputs, with up to M members, to be assigned to the outputs. The resultant R.times.M switch matrix will be smaller than an N.times.M switch matrix.

Deterministic method and an apparatus for minimal switch circuits

A programmable logic circuit having a routing matrix capable of providing 100% connectability and routability of a plurality of input signals to their appropriate configuration function blocks. In the present invention, input signals are first routed through the routing matrix before being processed by the input buffers. Thus, a slow user signal is processed by the relatively slow routing matrix before being provided with increased drive by the input buffers and passed on to the faster logical blocks. A number of programmable control bits are stored in SRAM. These control bits are decoded to determine which of the transmission gates of the routing matrix should be enabled. In this manner the input signal is routed to the appropriate configuration function block. Following the routing matrix is the input buffer. The highly driven output signal from the buffer is then passed to the configuration function block which performs the programmed logic functions on the signal.

Apparatus and method for selecting and buffering inputs of programmable

A product term allocation arrangement in which each of a first plurality of input conductors may be programmably joined to a first plurality of output conductors and to a first plurality of AND gates, a second plurality of input conductors may be programmably joined to a second plurality of output conductors and to a second plurality of AND gates, apparatus which may be selected to perform either an AND or an OR function connected to receive input signals from one of the first plurality of AND gates and one of the second plurality of AND gates, and a plurality of OR gates connected to receive input signals from a selected number of the apparatus connected to receive input signals from one of the first plurality of AND gates and one of the second plurality of AND gates.

User programmable product term width expander

A programmable logic device having the capability of initializing and resetting to a specified digital state. One or more clear/preset product terms are available for initializing and resetting the macrocells of the programmable logic device. Each macrocell can be either cleared to a '0' or preset to a '1' according to the clear/preset product terms. Control bits are used to select which of the clear/preset product terms, if any, are to be used to clear and/or preset a particular macrocell. These control bits are programmable for each of the macrocells, thereby allowing each macrocell to output either a '0' or a '1', as desired by the user, independent of the other macrocells. The macrocells can be cleared and preset asynchronously.

Programmable logic having selectable output states for initialization

A specialized output buffer circuit which obviates the need to utilize a separate multiplexer to determine polarity selection and output type selection in a programmable logic device is disclosed. In accordance with the present invention, these determinations are made in a specialized output buffer circuit. A sum of product term, a complement of the sum of product term, a registered version of the sum of product term, and a complement of the registered version of the sum of product term, are coupled directly to the output buffer circuit, wherein one of these signals is selected and coupled to an output pin.

Apparatus and method for selecting polarity and output type in a

In a programmable logic device having a plurality of gates capable of being programmed according to a plurality of product terms representing logic functions, an apparatus for allocating the product terms to a plurality of outputs. A first set of product terms are steerable to one of at least two outputs. A second set of product terms is permanently assigned to a predetermined output. The second set is comprised of more product terms than the first set, wherein the average number of product terms per output is low, yet a user has the flexibility of implementing logic functions requiring a relatively large number of product terms.

Apparatus and method for product term allocation in programmable logic

A programmable gate array comprised of a number of configurable functional blocks. Each configurable functional block has a number (m) of inputs. A global interconnect matrix interconnects the configurable functional blocks. The global interconnect matrix provides for routing any combination of signals entering the matrix to any configurable functional block, up to and including the maximum number (m) of inputs of a configurable functional block. Each configurable functional block includes a product term array connected to the m inputs. The product term array can perform a logical AND of up to m bits. A compare term array is also connected to the m inputs. The compare term array can perform an identity compare of up to m/2 bits. A number n of macro cells are provided in each configurable functional block wherein the number n is less that the number m. An allocation circuit allocates the outputs of the compare term array and the product terms to a macro cell, any compare term being allocable in place of a product term to the macro cell.

High-speed comparator logic for wide compares in programmable logic

An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

Semiconductor memory with a flag for indicating test mode

An EEPROM cell suitable for use in programmable logic devices contains three transistors. A floating gate transistor is used to retain a programmed value using charge storage on the floating gate. A read transistor is connected between the floating gate transistor and an output signal line, and used to access the value stored in the floating gate transistor. A write transistor is connected to the floating gate transistor opposite the read transistor, and is used when programming the floating gate transistor. The write transistor and its associated control circuitry are fabricated to handle the higher programming voltages required by the floating gate device. The read transistor and associated drive circuitry are not required to handle the higher programming voltages, and can be fabricated using smaller, faster devices.

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Southlake, TX, United States of America

Randy C Steele